STPM10 datasheet(22/51 Pages) STMICROELECTRONICS

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Theory of operation

STPM10

22/51

Doc ID 17728 Rev 3

When the secondary channel is selected to be integrated by the final energy integrator, the

MUX and INH signals change according to Figure 19 below.

This means that energy of four periods from secondary channel followed by energy of four

periods from primary channel is sampled within the tamper module. From these two

samples, called B and A respectively, the criteria of tamper is calculated and the channel

with higher current is selected, resulting in a new tamper state. If four consecutive new

results of criteria happen, i.e. after elapsed 5.12 s at 50 Hz, the meter will enter into tamper

state. Thus, the channel with the higher current will be selected for the energy calculation. If

samples of power A and B would have different signs, the Tamper would be on all the time

but, the channel with bigger power would be still selected for the final integration of energy.

If a tamper status has been detected, the multiplex ratio will be 56:8 if the primary channel

energy is greater than the secondary one, otherwise it will be 8:56.

The detected tamper condition is stored in the BIT status bit. If BIT = 0 tamper is not

detected, if BIT = 1 a tamper condition has been detected. In standalone mode the BIT flag

is also available in the SDATD pin.

7.10

Phase compensation

The STPM10 does not introduce any phase shift between the voltage and current channel.

However, the voltage and current signals come from transducers, which could have inherent

phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current

transformer (CT). These phase errors can vary from part to part, and they must be corrected

in order to perform accurate power calculations. The errors associated with phase mismatch

are particularly noticeable at low power factors. The STPM10 provides a means of digitally

calibrating these small phase errors by introducing delays on the voltage or current signal.

The amount of phase compensation can be set using the 4 bits of the phase calibration

The default value of this register is at a value of 0, which gives 0° phase compensation.

When the 4 bits give a CPH of 15 (1111) the compensation introduced is +0.576°. This

compensates the phase shift usually introduced by the current sensor, while the voltage

sensor, normally a resistor divider, does not introduce any delay. The resolution step of the

phase compensation is 0.038°.

7.11

Clock generator

All the internal timing of the STPM10 is based on the CLKOUT signal. This signal can be

generated in three different ways:

Figure 19.

Timings of tamper module - Secondary channel selected

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