STPM10 datasheet(33/51 Pages) STMICROELECTRONICS

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STPM10

Theory of operation

Doc ID 17728 Rev 3

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7.21

Reading data records

A microcontroller is able to read all measurement results and all system signals

(configuration, calibration, status, mode). Again, the time step can be as short as 30 ns.

There are two phases of reading, called latching and shifting.

Latching is used to sample results into transmission latches. The transmission latches are

the flip-flops that hold the data in the SPI interface. This is done with the active pulse on

SYN when SCS is idle. The length of the pulse on SYN must be longer than 2 periods of the

measurement clock, i.e. more than 500 ns at 4 MHz.

The shifting starts when SCS become active. In the beginning of this phase, another much

shorter pulse (30 ns) on SYN should be applied in order to ensure that an internal

transmission serial clock counter is reset to zero. An alternative way is to extend the pulse

on SYN into the second phase of reading. After this reset is done, a 32 serial clocks-per-

data record should be applied. Up to 8 data records can be read this way. This procedure

can be aborted at any time through deactivation of SCS (see Figure 24).

The first read-out byte of the data record is the least significant byte (LSB) of the data value

and, of course, the fourth byte is the most significant byte (MSB) of the data value. Each

byte can be further divided into a pair of 4-bit nibbles, referred to as the most and least

significant nibble (MSN, LSN). This division makes sense with the MSB of the data value

because its MSN holds the parity code rather than useful data.

The sequence of the data record during the read operation is fixed. Normally, an application

reads the 1st through the 6th data record; the 7th and 8th data record would be read only

when it needs to fetch the configuration data. However, an application may apply a

precharge command (see Table 12) prior to the reading phase. This command forces the

device to respond with the sequence 5th - 8th, 1st - 4th. Such a change of sequence can be

used to skip the first four data records.

The timing diagram of the reading operation is shown in Figure 24. One can see the latching

and beginning of the shifting phase of the first byte (0x5F) of the first data record, and the

end of reading. Also, both alternatives for resetting the internal transmission serial clock

counter are shown in signal SYN.

Figure 23.

Data record reconstruction

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