STPM10 datasheet(32/51 Pages) STMICROELECTRONICS

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Theory of operation

STPM10

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Doc ID 17728 Rev 3

clock signal. When SCS is high, SCL is also high, determining the idle state of the

SPI.

–

SDA: the data pin. If SCS is low, the operation of SDA is dependent on the status

of the SYN pin. If SYN is high, SDA is the output of the serial bit data (read mode).

If SYN is low, SDA is the input of the serial bit data signal (write mode). If SCS is

high, SDA is the input of the idle signal.

Any pin above has an internal weak pull-up mechanism of nominal 15 µA. This means that

when a pin is not forced by external signals, the state of the pin is logic high. A high state of

any input pin described above is considered an idle (not active) state. For the SPI to operate

correctly, the STPM10 must be correctly supplied as described in Section 7.6: Power supply.

An idle state of the SPI module is recognized when the signals of pins SYN, SCS, SCL and

SDA are in a logic high state. Any SPI operation should start from this idle state.

When SCS is active (low), signal SDATD should change its state at trailing edge of signal

SCLNLC and the signal SDATD should be stable at next leading edge of signal SCLNLC.

The first valid bit of SDATD is always started with activation of signal SCLNLC.

7.20

Remote reset

The timing diagram of this operation is shown in Figure 22. The time step can be as short as

30 ns.

The internal reset signal is called RRR. Unlike the POR, the RRR signal does not cause the

30 ms delayed restart of the analog module, and the 120 ms delay in the restart of the digital

module. This signal does not clear the mode signals.

Figure 22.

Timing for providing remote reset request (1)

All time intervals must be longer than 30 ns. t7 → t8 is the reset time; this interval must be longer than 30 ns also.

SCS

SYN

SCLNLC

SDATD

SCS

SYN

SCLNLC

SDATD

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