SPEAR1310 datasheet(23/57 Pages) STMICROELECTRONICS

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SPEAr1310

Giga/Fast Ethernet media access controller (GMAC)

Doc ID 17528 Rev 4

23/57

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Discards frames on late collision, excessive collisions, excessive deferral, and under-

run conditions

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Software control to flush TX FIFO

The DMA block exchanges data between the MTL block and host memory. The host can use

a set of registers (DMA CSR) to control the DMA operations. The DMA block supports the

following features:

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32-bit data transfers

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Single-channel transmit and receive engines

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Fully synchronous design operating on a single system clock (except for CSR module,

when a separate CSR clock is configured)

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Optimization for packet-oriented DMA transfers with frame delimiters

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Byte-aligned addressing for data buffer support

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Dual-buffer (ring) or linked-list (chained) descriptor chaining

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Descriptor architecture that allows large blocks of data transfer with minimum CPU

intervention

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Comprehensive status reporting for normal operation and transfers with errors

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Individual programmable burst size for transmit and receive DMA engines for optimal

host bus utilization

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Programmable interrupt options for different operational conditions

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Complete per-frame transmit/receive interrupt control

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Round-robin or fixed-priority arbitration between receive and transmit engines

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Start/stop modes

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Separate ports for host CSR access and host data interface

The GMAC audio video (AV) feature enables transmission of time-sensitive traffic over

bridged local area networks (LANs). The GMAC AV has the following features:

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Compliant to IEEE 802.1-AS standard, version D6.0: specifies the protocol and

procedures used to ensure that the synchronization requirements are met for time-

sensitive applications

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Compliant to IEEE 802.1-Qav standard, version D6.0: allows the bridges to provide

time-sensitive and loss-sensitive real-time audio video data transmission (AV traffic). It

specifies the priority regeneration and controlled bandwidth queue draining algorithms

that are used in bridges and AV traffic sources

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Supports one additional channel (channel 1) on the transmit and receive paths for AV

traffic in 100 Mbps and 1000 Mbps modes. The channel 0 is available by default and

carries the legacy best-effort Ethernet traffic on the transmit side

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Supports IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for the

additional transmit channels

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Provides separate DMA, TxFIFO, and RxFIFO MTL for the additional channel (to avoid

"head of line blocking" issues); the system-side interface remains the same

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