SPEAR1310 datasheet(51/57 Pages) STMICROELECTRONICS

51 / 57 page

SPEAr1310

Direct memory access controller (DMAC)

Doc ID 17528 Rev 4

51/57

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Programmable maximum burst transfer size per channel

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Maximum transaction size configured to 256 for all the channels

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Maximum block size configured to 4095 for all the channels

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Bus locking – can be programmed to be over the transaction, block, or DMA transfer

level

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Channel locking – can be programmed to be over the transaction, block, or DMA

transfer level

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16 Handshaking interfaces for source and destination peripherals

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Hardware and Software handshaking interfaces

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Peripheral interrupt handshaking interface

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Handshaking interface supports single or burst DMA transactions

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Polarity control for hardware handshaking interface

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Enabling and disabling of individual DMA handshaking interface

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Programmable flow control at block transfer level (source, destination or DMAC core)

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Software control of source data pre-fetch when destination is flow controller

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Combined and separate interrupt requests

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Interrupt generation on DMA transfer (multiblock) completion, block transfer

completion, single and burst transaction completion and error condition

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Support of interrupt enabling and masking.

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