SPEAR1340 datasheet(7/200 Pages) STMICROELECTRONICS

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SPEAr1340

Device functions

Doc ID 023063 Rev 4

7/200

Device functions

2.1

CPU subsystem

The CPU subsystem is based on the ARM Cortex A9 processor, and has a dual-core

configuration.

Main features:

Each core has the following features:

●

ARM v7 CPU at 600 MHz

●

32 KB of L1 instruction CACHE with parity check

●

32 KB of L1 data CACHE with parity check

●

Embedded FPU for single and double data precision scalar floating-point operations

●

Memory management unit (MMU)

●

ARM, Thumb2 and Thumb2-EE instruction set support

●

Program Trace Macrocell (PTM) and CoreSight© component for software debug

●

32-bit timer with 8-bit prescaler

●

Internal watchdog (working also as timer)

The dual core configuration is completed by a common set of components:

●

Snoop control unit (SCU) to manage inter-process communication, cache-to-cache and

system memory transfer, cache coherency

●

Generic interrupt control (GIC) unit configured to support 128 independent interrupt

sources with software configurable priority and routing between the two cores

●

64-bit global timer with 8-bit prescaler

●

Accelerator coherence port (ACP)

●

Parity support to detect runtime failures for other internal memories

●

512 KB of unified 8-way set associative L2 cache with support for ECC

●

L2 Cache controller based on PL310 IP released by ARM

●

Dual asynchronous 64-bit AMBA 3 AXI interface with possible filtering on the second

one to use a single port for DDR memory access

●

JTAG interface and Trace port: debug and trace can be inhibited through OTP

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