SPEAR1340 datasheet(10/200 Pages) STMICROELECTRONICS

10 / 200 page

Device functions

SPEAr1340

10/200

Doc ID 023063 Rev 4

2.6

Flexible static memory controller (FSMC)

The flexible static memory controller enables to interface external parallel Flash memories

as well as static RAMs.

Main features:

●

Support for parallel NAND Flash:

–

8-bit or 16-bit data bus

–

2 chip select signals

–

no limitation on NAND capacity (number of pages)

–

hardware ECC (error correction code) support, correcting up to 8 errors per page

(512 bytes wide)

–

support for SLC (single-level cell) and MLC (multi-level cell) Flash devices, as far

as compatible with available ECC features

●

Support for parallel NOR Flash:

–

8-bit or 16-bit data bus

–

26-bit address bus

–

2 chip select (CS) signals

–

Maximum capacity is 64 MB for each CS, hence up to 128 MB with 2 external

Flash devices

●

Support for asynchronous static RAMs (SRAMs):

–

8-bit or 16-bit data bus

–

26-bit address bus

–

2 chip select (CS) signals

–

Maximum capacity is 64 MB for each CS, hence up to 128 MB with 2 external

SRAM devices

●

Support for multiplexed NOR and SRAM

●

Write FIFO: 16 words depth, each word is 32 bits wide

●

Independent read/write timings and protocol, allowing matching the widest variety of

memories and timings

●

Wait signal for timings handshake

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