SPEAR1340 datasheet(13/200 Pages) STMICROELECTRONICS

13 / 200 page

SPEAr1340

Device functions

Doc ID 023063 Rev 4

13/200

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An enhanced module to calculate and insert IPv4 header checksum and TCP, UDP, or

ICMP checksum in frames transmitted in store-and-forward mode.

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A module to support Ethernet frame time stamping as described in IEEE 1588- 2002

and IEEE 1588-2008 (standard for precision networked clock synchronization). Sixty-

four-bit time stamps are given in the transmit or receive status of each frame.

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MDIO master interface for PHY device configuration and management: station

management agent (SMA), MDIO module

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Supports the standard IEEE P802.3az, version D2.0 for energy efficient Ethernet;

allows physical layers to operate in the low-power idle (LPI) mode

The MAC transaction level (MTL) block consists of two sets of FIFOs: a transmit FIFO

with programmable threshold capability, and a receive FIFO with a programmable threshold

(default of 64 bytes). The MTL block has the following features:

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32-bit transaction layer block that provides a bridge between the application and the

GMAC

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Single-channel transmit and receive engines

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Synchronization for all clocks in the design (transmit, receive, and system clocks)

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Optimization for packet-oriented transfers with frame delimiters

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Four separate ports for system-side and GMAC side transmission and reception

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FIFO instantiation outside the top-level module to facilitate memory testing/instantiation

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4 KB receive FIFO size on reception

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Supports receive status vectors insertion into the receive FIFO after the EOF transfer.

This enables multiple-frame storage in the receive FIFO without requiring another FIFO

to store those frames

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Configurable receive FIFO threshold (default fixed at 64 bytes) in cut-through or

threshold mode

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Provides an option to filter all error frames on reception and not forward them to the

application in store-and-forward mode.

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Provides an option to forward under-sized good frames

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Supports statistics by generating pulses for frames dropped or corrupted (due to

overflow) in the receive FIFO

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2 KB FIFO size on transmission

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Store and forward mechanism for transmission to the GMAC

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Threshold control for transmit buffer management

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Automatic retransmission of collision frames for transmission

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Discards frames on late collision, excessive collisions, excessive deferral, and under-

run conditions

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Software control to flush TX FIFO

The DMA block exchanges data between the MTL block and host memory. The host can

use a set of registers (DMA CSR) to control the DMA operations. The DMA block supports

the following features:

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32-bit data transfers

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Single-channel transmit and receive engines

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Fully synchronous design operating on a single system clock (except for CSR module,

when a separate CSR clock is configured)

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Optimization for packet-oriented DMA transfers with frame delimiters

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