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SPEAR1340 数据表(PDF) 31 Page - STMicroelectronics

部件名 SPEAR1340
功能描述  Dual-core Cortex A9 HMI embedded MPU
PDF  200 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

SPEAR1340 数据表(HTML) 31 Page - STMicroelectronics

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SPEAr1340
Device functions
Doc ID 023063 Rev 4
31/200
Main features:
●
AMBA APB interface
●
GPIO or keyboard functionality with selection of any one of the two keyboard matrices:
–
12-bit general purpose parallel port (GPIO) with input or output single pin
programmability
–
36 (6x6) keys keyboard
–
4 (2x2) key keyboard plus 8-bit GPIO with input or output single pin
programmability
2.29
Cryptographic co-processor (C3)
C3 is a multipurpose, instruction driven, programmable DMA-based co-processor. It is
configured to accelerate cryptographic and network security functions.
Main features:
●
AMBA AHB 2.0 master and slave interfaces
●
Scatter and gather DMA engine (implemented only by MPCM channel)
●
Instruction dispatchers
–
ID0 and ID1 available
–
ID2 and ID3 not available
●
Internal RAM: 4Kx32
●
Coupling/Chaining: 2 paths
The hardware accelerator crypto algorithms available in SPEAr1340 have the following
channels supported by mentioned operations:
●
Channel 0: Move channel
–
Supported operations: copy, AND, OR, XOR
–
Chained mode: either master or slave
–
Cascaded mode: both master and slave
–
Input FIFO: 8x32 bits
–
Output FIFO: 8x32 bits
●
Channel 1: Data encryption standard (DES and TripleDES)
–
ID: 0x00002001
–
Supported algorithms: DES (56-bit keys, ECB and CBC encryption/decryption, no
parity check) and TripleDES (168-bit keys, ECB and CBC encryption/decryption,
EncDecEnc)
–
Input FIFO: 16x32 bits
–
Output FIFO: 16x32 bits
●
Channel 2: MPCM for the advanced encryption standard (AES)
–
ID: 0x0000E000
–
Supported algorithms: AES (128-, 192-, 256-bit keys, ECB and CBC
encryption/decryption, with programmable operation modes to support almost all
possible modes, including Counter and XTS mode)
–
Memory for modes of operation: 512 words of 62 bits each
–
Input FIFO: 16x32 bits



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