SPEAR1340 datasheet(36/200 Pages) STMICROELECTRONICS

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Device functions

SPEAr1340

36/200

Doc ID 023063 Rev 4

2.34

Clock and reset system

This centralized structure provides system synchronization.

Main features:

●

Six PLLs. Four of them are fully programmable and offer an EMI reduction mode

(spread spectrum clock generation through dithering) that can replace all traditional

EMI reduction techniques.

–

PLL1 programmable dithered pll, dedicated for Core1 & 2 & AXI/AHB bus &

peripherals. Both core need to run at the same speed

–

PLL2 programmable dithered PLL, dedicated for the 125 MHz clock of the Gigabit

Ethernet MAC

–

PLL3 programmable dithered PLL, for specific embedded IP functions

–

PLL4 programmable dithered PLL, dedicated for the DDR memory controller

(Asynchronous access memory mode)

–

PLL5 low jitter, dedicated for the USB

–

PLL6 for the PCIe controllers

●

Several synthesizers provide different frequencies for different IPs

●

Fully programmable control of clock and reset signals for all slave blocks allowing

sophisticated power management.

2.35

Reset and clock generator (RCG)

The reset and clock generator (RCG) provides the system clocks and resets. It is highly

configurable through the miscellaneous registers.

Main features:

●

Three main clock sources:

–

osci1: 24 MHz clock coming from internal oscillator connected to external quartz

–

osci2: 32 kHz clock coming from internal oscillator used for RTC block (optional)

–

osci3: 25/100 MHz clock coming from MIPHY macro (optional)

●

Three programmable dithered PLLs (to reduce EMI):

–

PLL1: primarily used to generate the 1 GHz clock for the AMBA subsystem

–

PLL2, PLL3: primarily used to generate clocks for generic IPs

●

Seven configurable clock generators:

–

SSCG1-4: used by generic IPs

–SSCG5: for CPU clock

–

SSCG6: for CLCD clock

–

SSCG7: for AHB, APB clocks

●

Three operating modes for AMBA clocks:

–

DOZE: the clock source is osci2 (osci1 after power on)

–

SLOW: the clock source is the osci1 or a divided version

–

NORMAL: the clock source is PLL1 (by default), PLL2, PLL3 or SSCG7

●

Configurable clock gating and software reset for most peripherals

●

Global software reset and watchdog reset

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