M95320-R datasheet(20/48 Pages) STMICROELECTRONICS

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Instructions

M95320-W M95320-R M95320-DR

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Doc ID 5711 Rev 14

6.3.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal enable the device to be put in the Hardware Protected mode (when the Status

mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits

and the Write Status Register (WRSR) instruction is no longer accepted for execution.

6.4

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction is used to write new values to the Status

previously executed.

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,

followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)

driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that

latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).

Otherwise, the Write Status Register (WRSR) instruction is not executed.

The instruction sequence is shown in Figure 10.

Figure 10.

Write Status Register (WRSR) sequence

Table 6.

Status Register format

SRWD

BP1

BP0

WEL

WIP

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

AI02282D

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

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