M95320-R datasheet(24/48 Pages) STMICROELECTRONICS

24 / 48 page

Instructions

M95320-W M95320-R M95320-DR

24/48

Doc ID 5711 Rev 14

The instruction is not accepted, and is not executed, under the following conditions:

●

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before),

●

if a Write cycle is already in progress,

●

if the device has not been deselected, by driving high Chip Select (S), at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in),

●

if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

Note:

The self-timed write cycle tW is internally executed as a sequence of two consecutive

events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is

read as “0” and a programmed bit is read as “1”.

Figure 13.

Page Write (WRITE) sequence

Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.

AI01796D

35 36 37 38 39 40 41 42

44 45 46 47

3456789 10

20 21 22 23 24 25 26 27

14 13

3210

28 29 30

Instruction

16-Bit Address

765432

Data Byte 1

765432

Data Byte 2

765432

Data Byte 3

65432

Data Byte N

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