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M95320-R 数据表(PDF) 30 Page - STMicroelectronics

部件名 M95320-R
功能描述  32-Kbit serial SPI bus EEPROM with high-speed clock
PDF  48 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M95320-R 数据表(HTML) 30 Page - STMicroelectronics

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Power-up and delivery state
M95320-W M95320-R M95320-DR
30/48
Doc ID 5711 Rev 14
7
Power-up and delivery state
7.1
Power-up state
After power-up, the device is in the following state:
●
Standby power mode,
●
deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
●
not in the Hold condition,
●
the Write Enable Latch (WEL) is reset to 0,
●
Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.



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