WM8213SCDSSLASHV datasheet(33/38 Pages) WOLFSON

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Production Data

WM8213

PD Rev 4.1 July 2008

ADDRESS

<A5:A0>

BIT

NAME(S)

DEFAULT

DESCRIPTION

3:0

RLCDAC[3:0]

1111

Controls RLCDAC driving VRLC/VBIAS pin to define single ended

signal reference voltage or Reset Level Clamp voltage. See

Electrical Characteristics section for ranges.

5:4

CDSREF[1:0]

When LEGACY=0 these register bits have no effect.

CDS mode reset timing adjust.

00 = Advance reset sample by 1 MCLK period (relative to

default).

01 = Default reset sample position.

10 = Delay reset sample by 1 MCLK period (relative to default)

11 = Delay reset sample by 2 MCLK periods (relative to default)

When MONO=0 these register bits have no effect

Monochrome mode channel select.

000011

(03h)

Setup

7:6

CHAN[1:0]

00 = Red channel select

01 = Green channel select

10 = Blue channel select

11 = Reserved

000100

(04h)

Software

Reset

Any write to Software Reset causes all cells to be reset. It is

recommended that a software reset be performed after a power-

up before any other register writes.

000101

(05h)

Auto-cycle

Reset

Any write to Auto-cycle Reset causes the auto-cycle counter to

reset

to RINP. This function is only required when LINEBYLINE = 1.

LINEBYLINE

Selects line by line operation. Line by line operation is intended

for use with systems which operate one line at a time but with up

to three colours shared on that one output.

0 = normal operation,

1 = line by line operation.

When line by line operation is selected MONO is forced to 1 and

CHAN[1:0] to 00 internally, ensuring that the correct internal

timing signals are produced. Green and Blue PGAs are also

disabled to save power.

ACYC

When LINEBYLINE = 0 this bit has no effect.

When LINEBYLINE = 1 this bit determines the function of the

RSMP input pin and the offset/gain register controls.

0 = RSMP pin enabled for either reset sampling (CDS) or Reset

Level Clamp control. Internal selection of gain/offset multiplexers

using INTM[1:0] register bits.

1 = Auto-cycling enabled by pulsing the RSMP input pin. This

means that each time a pulse is applied to this pin the single

input channel will switch to the next offset register and gain

Red->Green->Blue->Red… offset and gain registers applied to

the red input channel.

When auto-cycling is enabled, the RSMP pin cannot be used to

control reset level clamping. The CLMPCTRL bit may be used

instead (enabled when high, disabled when low).

NB, when auto-cycling is enabled, the RSMP pin cannot be used

for reset sampling (i.e. CDS must be set to 0).

3:2

INTM[1:0]

When LINEBYLINE=0 or ACYC=1 this bit has no effect.

When LINEBYLINE=1 and ACYC=0:

Controls the PGA/offset mux selector:

00 = Red PGA/Offset registers applied to input channel

01 = Green PGA/Offset registers applied to input channel

10 = Blue PGA/Offset registers applied to input channel

11 = Reserved.

000110

(06h)

Setup

7:4

Reserved

0000

Must be set to 0

WM8213SCDS/V 数据表(PDF) 33 Page - Wolfson Microelectronics plc

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