Production Data

WM8213

w

PD Rev 4.1 July 2008

17

Table 2 summarises the various options for control of the Reset Level Clamp switch.

RLCEN

LEGACY CLAMPCTRL

LINEBYLINE

&&ACYC

OUTCOME

USE

0

X

X

X

RLC is not enabled. RLC switch is always open.

When input is DC coupled and

within supply rails.

1

0

0

X

RLC switch is controlled directly from RSMP input

pin:

RSMP=0: switch is open

RMSP=1: switch is closed

When user explicitly provides a

reset sample signal and the

input video waveform has a

suitable reset level.

1

0

1

X

VSMP applied as normal, RSMP is used to indicate

the location of black pixels

RLC switch is controlled by logical combination of

RSMP and VSMP:

RSMP && VSMP = 0: switch is open

RSMP && VSMP = 1: switch is closed

When you wish to clamp during

the video period of black pixels

or there is no stable per-pixel

reference level.

1

1

X

X

LEGACY mode RLC works in the same fashion as

the WM819x series, where the RSMP pin is

equivalent to the RLC/ACYC pin on those devices.

The reset sample clock which is generated by the

LEGACY internal timing generator is gated with the

RSMP pin to produce the RLC control signal CL

(see Figure 11) :

CL=0: clamp switch open

CL=1: clamp switch closed

When using the LEGACY

timing mode.

0

X

1

1

1

In this mode the RSMP pin is used to control auto-

cycling so can’t be used for clamp control.

Register bit CLAMPCTRL controls whether RLC is

enabled or not.

CLAMPCTRL=0, RLC is disabled

CLAMPCTRL=1, RLC is enabled and

every pixel will be clamped during the

control signal CL (see Figure 11).

When auto-cycling in LEGACY

mode.

Table 2 Reset Level Clamp Control Summary

CDS/NON-CDS PROCESSING

For CCD type input signals, containing a fixed reference/reset level, the signal may be processed

using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise.

With CDS processing the input waveform is sampled at two different points in time for each pixel,

once during the reference/reset level and once during the video level. To sample using CDS, register

bit CDS must be set to 1 (default). This causes the signal reference to come from the video reference

level as shown in Figure 12.

The video sample is always taken on the falling edge of the input VSMP signal (VS). In CDS-mode

the reset level is sampled on the falling edge of the RSMP input signal (RS).

For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS

processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on

pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled at the same time as VSMP samples the

video level in this mode.

VSMP has gone low (VS) regardless of the operating mode. If in non-CDS mode (CDS=0) the

voltage on the VRLC/VBIAS pin is also sampled at this point. In CDS-mode (CDS=1) the position of

the reset sample (RS) can be varied, under control of the CDSREF[1:0] register bits, as shown in

Figure 11.