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WM8213SCDS/V 数据表(PDF) 32 Page - Wolfson Microelectronics plc

部件名 WM8213SCDS/V
功能描述  24MSPS 16-bit CCD Digitiser
PDF  38 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8213SCDS/V 数据表(HTML) 32 Page - Wolfson Microelectronics plc

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WM8213
Production Data
w
PD Rev 4.1 July 2008
32
ADDRESS
<A5:A0>
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
1:0
OPFORM[1:0]
0
Determines the output data format.
x0 = 8-bit multiplexed (8+8 bits)
01 = 8-bit parallel (8-MSBs only)
11 = 4-bit multiplexed mode (4+4+4+4 bits). This mode is only
valid when LEGACY=1.
2
INVOP
0
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output,
1 = negative-going video gives positive going output data.
Output Disable. This works with the OEB pin to control the output
pins.
0=Digital outputs enabled, 1=Digital outputs high impedance
OEB (pin)
OPD
OP pins
0
0
Enabled
0
1
High Impedance
1
0
High Impedance
3
OPD
0
1
1
High impedance
4
LOWREFS
0
Reduces the ADC reference range (2*[VRT-VRB]), thus changing
the max/min input voltages.
0= ADC reference range = 2.0V
1= ADC reference range = 1.2V
5
RLCDACRNG
1
Sets the output range of the RLCDAC.
0 = RLCDAC ranges from 0 to AVDD (approximately),
1 = RLCDAC ranges from 0 to VRT (approximately).
Controls the latency from sample to data appearing on output
pins
Latency
DEL
LEGACY=0
All timing modes
LEGACY=1
timing modes 1-2,4-6
LEGACY
=1
timing
mode 3
00
7 MCLK periods
16.5 MCLK periods
23.5
MCLK
periods
01
8 MCLK periods
18.5 MCLK periods
26.5
MCLK
periods
10
9 MCLK periods
20.5 MCLK periods
29.5
MCLK
periods
000010
(02h)
Setup
Register 2
7:6
DEL[1:0]
00
11
10 MCLK periods
22.5 MCLK periods
31.5
MCLK
periods



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