WM8213

Production Data

w

PD Rev 4.1 July 2008

18

CONTROL

INTERFACE

C

IN

RINP

or

GINP

or

BINP

VRLC/

VBIAS

VRLCDACPD

4-BIT

RLCDAC

RLCDAC[3:0]

closed=

50 Ohm

RLC

switch

CLMP

VS

RS (if CDS=1) or

VS (if CDS=0)

CDS

CDS=1

CDS=0

'Video'

sample

capacitor

'Reference'

sample

capacitor

Figure 12 CDS/non-CDS Input Configuration

OFFSET ADJUST AND PROGRAMMABLE GAIN

The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset

DAC to compensate for offsets and then amplified by a 9-bit PGA. The gain and offset for each

channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].

The gain characteristic of the WM8213 PGA is shown in Figure 13. Figure 14 shows the maximum

device input voltage that can be gained up to match the ADC full-scale input range (default=2V).

In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order

(Red

→ Green → Blue → Red…) by pulsing the RSMP pin, or controlled via the ACYC and

INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.