WM8213SCDSSLASHV datasheet(34/38 Pages) WOLFSON

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WM8213

Production Data

PD Rev 4.1 July 2008

ADDRESS

<A5:A0>

BIT

NAME(S)

DEFAULT

DESCRIPTION

REDPD

When set powers down red S/H, PGA

GRNPD

When set powers down green S/H, PGA

BLUPD

When set powers down blue S/H, PGA

ADCPD

When set powers down ADC. Allows reduced power

consumption without powering down the references which have a

long time constant when switching on/off due to the external

decoupling capacitors.

VRLCDACPD

When set powers down 4-bit RLCDAC, setting the output to a

high impedance state and allowing an external reference to be

driven in on the VRLC/VBIAS pin.

ADCREFPD

When set disables VRT, VRB buffers to allow external references

to be used.

VRXPD

When set disables VRX buffer to allow an external reference to

be used.

000111

(07h)

Setup

Reserved

Must be set to 0

VSMPDET

When LEGACY=0 this register bit has no effect.

When LEGACY=1:

0 = Normal operation, signal on VSMP input pin is applied directly

to Timing Control block.

1 = Programmable VSMP detect circuit is enabled. An internal

synchronisation pulse is generated from signal applied to VSMP

input pin and is applied to Timing Control block in place of VSMP.

3:1

VDEL[2:0]

000

When LEGACY=0 or VSMPDET=0 these bits have no effect.

The VDEL bits set a programmable delay from the detected edge

of the signal applied to the VSMP pin. The internally generated

pulse is delayed by VDEL MCLK periods from the detected edge.

See Figure 20, Internal VSMP Pulses Generated for details.

POSNNEG

When LEGACY=0 or VSMPDET=0 this bit has no effect.

When LEGACY=1 and VSMPDET=1 this bit controls whether

positive or negative edges on the VSMP input pin are detected:

0 = Negative edge on VSMP pin is detected and used to generate

internal timing pulse.

1 = Positive edge on VSMP pin is detected and used to generate

internal timing pulse.

See Figure 20 for further details.

RLCEN

Reset Level Clamp Enable. When set Reset Level Clamping is

enabled. The method of clamping is determined by CLAMPCTRL

and LEGACY.

In LEGACY mode clamping will still occur on every pixel at a time

defined by the CDSREF[1:0] bits.

CLAMPCTRL

This bit has no effect if LEGACY=1. See Table 2 for more

information.

0 = RLC switch is controlled directly from RSMP input pin:

RSMP = 0: switch is open

RMSP = 1: switch is closed

1 = RLC switch is controlled by logical combination of RSMP and

VSMP.

RSMP && VSMP = 0: switch is open

RSMP && VSMP = 1: switch is closed

001000

(08h)

Setup

Reserved

Must be set to 0

WM8213SCDS/V 数据表(PDF) 34 Page - Wolfson Microelectronics plc

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