comp

+

-

2.5V

VREF

PORN

ResTh

R1

R2

R3

R1=R2=R3=appr.25k

VDD

VSS

VSS

VDD

Ra

Rb

k=Rb / (Ra+Rb)

Off-Delay

porv

Vth =

2*VREF

1+k

with Ra, Rb << R1,R2,R3:

VDD

porv

PORN

300ms

Rhyst=appr.290k

With V(ResTh) defined by external resistors much smaller than R1-3, the POR- threshold can

be set in the range of 2.5V to 5.0V according to the given equation.

1.1.3 TIMING

MCLK: The circuit gets clocked by an 11.0592MHz MASTER CLOCK from external which

is the frequency reference for all RX and TX functions. Since this circuit is working as a

narrow band FSK-modem, the precision of this clock is very critical.

CKSYS: The master-clock divided by 2 is presented at the output CKSYS. In test-mode1 this

pin is used to measure the FSK_ZC signal. In test-mode 2 this pin is used to measure the

PLL-output SC-CLK. In test-mode 3 this pin is used to measure the PLL-output Fmixer.

TxEnI: Transmission gets initialized by setting the input signal TxEn to low. When ZCEN

(zero-crossing TX-sync) is disabled, the internal signal TxEnI is following and setting the

TX-driver active immediately. When ZCEN is enabled, the signal TxEnI is set to low after

the high-going edge of ZC-input after TxEn was forced low.

TxEn

ZC

CKR/T

valid

valid

valid

valid

RXD

TXD

receive

transmit

TxEnI

CKTX

TXD-input gets strobed by CKR/T in TxSyn-mode which can be entered with setting D7 of

the TST-Reg. to H. In default mode (asynchr. TXD) the CKR/T gets synchronised by

TXD-edges with a clock 64 times the baud-rate.

TX-TIMEOUT: There is a timeout-function implemented which sets the device back to

receive-mode (TxEnI=H) after 3 seconds of transmission. This timeout-function can be

disabled by setting the contol-bit MMV by the serial interface. In test-mode 2 and 3 the 3sec

timeout is divided by 256 to 11.7ms to reduce test-time.

AS5501 / AS5502 Multimode Powerline Modem

Data Sheet

Rev A, May 2000

Page 7/25