6.14 Carrier Detect - Test

VDD=5.0V, input: RXIN, output: CD

min

typ

max

Condition

-

-

4.9mVeff

M82

2.9mVeff

-

-

M82

8.0ms

8.33ms

9.0ms

M82, FCDON=H

4.0ms

4.17ms

4.5ms

M132, FCDON=L

1.9ms

2.08ms

2.5ms

M132, FCDON=H

8.0ms

-

9.0ms

M82

4.0ms

-

5.0ms

M82, BD1,2=H,L

1.9ms

-

2.5ms

M82, BD1,2=H,H

6.15 CKRX - Test (pattern test)

The DPLL of the Rx-clock recovery circuit will be tested by a digital pattern defined during

design-phase. In Test-Mode 3 a certain DPLL-input will be supplied by the pin TST-IN. The

CLR/T has to recover a minimum of 20% jitter and a frequency tolerance of +/-1.5%.

6.16 Serial Interface - Test (pattern test)

The serial interface will be tested by a digital pattern defined during design-phase.

min

typ

max

Condition

Tspick

1us

-

-

-

Tcssu, Tcshd

200ns

-

-

-

Tdsu, Tdhd

100ns

-

-

-

Copyright

© 2000, Austria Mikro Systeme International AG, SchloB Premstatten, 8141 Unterpremstatten, Austria.Tel. +43-

(0)3136-500-0, Fax +43-(0)3136-52501, E-Mail info@amsint.com

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by

any means, without the prior permission in writing by the copyright holder. To the best of its knowledge, Austria Mikro Systeme

International asserts that the information contained in this publication is accurate and correct.

AS5501 / AS5502 Multimode Powerline Modem

Data Sheet

Rev A, May 2000

Page 25/25