Fin/Fbaud

typ. Gain

0.75

-3.0dB

1.3

-25dB

A comparator with hysteresis of appr. 200mV and adjustable (bias-distortion wafer-sort-trim)

absolute reference is converting the DataFilter-output to RXDA (asynchronous receive data).

1.3.6 Bit Error Rate

The system specification of BER is the following:

Parameter

Condition

min

typ

max

BER1 Bit Error Rate with

Minimum Input Level

White Noise with S/N=13dB

RXL = 1.5mVrms

5*10

-5

10

-3

BER3 Bit Error Rate with

Maximum Input Level

White Noise with S/N=25dB

RXL = 1.5Vrms

10

-7

10

-3

BER4 Bit Error Rate with

Medium Input Level

White Noise with S/N=13dB

RXL = 600mVrms

10

-6

10

-3

BER5 Bit Error Rate with

Impulsive Noise

Noise: 5Vpp rect., 100Hz,

DC=10%, Trise/fall=10us;

RXL=90mVrms

10

-3

BER6 Bit Error Rate with

Modulated Sinusoidal Noise

Noise: sine carrier w. 80% AM;

Fmod=1kHz, special S/N-Mask

RXL=1.5Vrms

10

-3

1.3.7 CKR-GEN

There is a digital pll for receive-clock reconstruction. The signal RXDA (async. RXD) gets

synchronised by this clock which then gives the synchronous receive data signal RXD.

A multiplexer is used to select RXDA or RXD to be transferred to the pin RXD by the use of

a control bit "ASYN". The signal RXDA is used to verify the Mixer and DataFil-structure.

A second multiplexer selects CKRX or CKTX to be transferred to pin CLKR/T by the use of

control signal "TxEn". In synchronouse-mode RXD is valid at the high going edge of

CKR/T.

1.4 TEST-MUX

A test-input pin, a test-output pin with attached buffer and multiplexers are used to have

access to some internal nodes for testing. To have access to internal nodes of the receiver in

normal receive operation, the bit TEST_D6 can be set to H for avoiding TST_IN function.

The asic is forced to one of these test-modes by setting the control-bits TEST1 and TEST2.

Test1 Test2 Mux-State

TST-IN

TST-OUT CKSYS Reset-Delay TX-Timeout

0

0

0

bypass timer

VREF

MCLK/2

300ms

3sec

1

0

1

IFI

IFO

FSK_ZC

300ms

3sec

0

1

2

TXI

RXO

SC-CLK

1.17ms

11.7ms

1

1

3

DPLL-IN

DFO

Fmixer

1.17ms

11.7ms

Mux-State 0 (Normal Operation): In normal operation the test-muxes are in position 0. In

this configuration, the reference voltage VREF (2.5V) is present at pin TST-OUT.

In this mode the reset and TX-timeout counter are bypassed with TST-IN set to H.

AS5501 / AS5502 Multimode Powerline Modem

Data Sheet

Rev A, May 2000

Page 16/25