1.1 SERIF, RESET, TIMING

SERIAL INTERFACE

SD-OUT

SD-IN

A0/CS

SCLK

Control Register Output

POR

BAND GAP REF.

TIMING

VREF

RESN

RES-TH

MCLK

CKSYS

Test1,2

SC-CLK

mux

CONTROL REGISTERS

Default Setting Rom

TXEN

ZC

BD1,2, ZCEN, MMV

TXENI

CKTX

IF-SCCLK

Fmixer

Mclk/2

1.1.1 SERIAL INTERFACE

There is a serial interface implemented for setting the control bits by a CPU.

Three bytes are available with following definitions and default contents (after reset).

Reg.-Name addr

D1

D2

D3

D4

D5

D6

D7

D8

MRK-REG

(def. value)

00H

MRK1

1

MRK2

0

MRK3

1

MRK4

0

MRK5

0

MRK6

0

MRK7

1

MRK8

1

GLOBAL

(def. value)

01H

MRK9

1

BD1

1

BD2

1

RxBw1

1

RxBw2

0

ZCEN

1

MMV

0

PWD

0

TEST

02H

TEST1

TEST2

ASYN

AgcH

digMix

noTSTin

TxSyn

FCdOn

(The default setting of the register "TEST" is always 00h.)

Bit-Name

Function

default val.

default function

MRK1-9

defines TX Mark Frequency (63.9k-140.55kHz)

453

131.85kHz

BD1,2

defines Baud-Rate and Modulation-Depth

1, 1

2400Hz/1200Hz

RXBW1,2

defines RX-BandPassFilter Bandwidth

1, 0

4.8kHz @132.45kHz

ZCEN

disable ZeroCrossing TX-Sync

1

ZC-disabled

MMV

disables transmit Timeout

0

TimeOut enabled

PWD

enables power down mode

0

powered up

TEST1,2

enables Test Mode 1-3

0, 0

normal mode

ASYN

disable synchronized receive data RXD

0

sync. RXD

AgcH

hold AGC counter-state

0

AGC-loop active

digMix

enables digital mixer; analog mixer enabled by def.

0

analog mixer

noTSTin

TST-out function only for receiver debugging

0

TSTin&out availab.

TxSyn

enables TXD sampling with CLR/T rising-edge

0

CLR/T gets synchronised

by TXD-edges

FCdOn

enables faster CD-ON timing (5/Bdrate)

0

Tcdon=(10/Bdrate)

AS5501 / AS5502 Multimode Powerline Modem

Data Sheet

Rev A, May 2000

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