AD7450ARM datasheet(18/24 Pages) AD

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PRELIMINARY TECHNICAL DATA

–18–

AD7450

Figure 20. Serial Interface Timing example

tQUIET

CONVERT

ACQUISITION

12.5(1/fSCLK)

1/Throughput

10ns

SCLK

This 664ns satisfies the requirement of 275ns for tACQ.

From Figure 20, tACQ comprises of:

2.5(1/FSCLK) + t8 + tQUIET

where t8 = 45ns. This allows a value of 119ns for tQUIET

satisfying the minimum requirement of 100ns.

As in this example and with other slower clock values, the

signal may already be acquired before the conversion is

complete but it is still necessary to leave 100ns minimum

tQUIET between conversions. In example 2 the signal should

be fully acquired at approximately point C in Figure 20.

MODES OF OPERATION

The mode of operation of the AD7450 is selected by

controlling the logic state of the

CS signal during a

conversion.

There are two possible modes of operation,

Normal Mode and Power-Down Mode. The point at which

CS is pulled high after the conversion has been initiated will

determine whether or not the AD7450 will enter the power-

down mode.

Similarly, if already in power-down,

controls whether the device will return to normal operation

or remain in power-down.

These modes of operation are

designed to provide flexible power management options.

These options can be chosen to optimize the power dissipa-

tion/throughput

rate

ratio

for

differing

application

requirements.

Normal Mode

This mode is intended for fastest throughput rate perfor-

mance.

The user does not have to worry about any

power-up times as the AD7450 is kept fully powered up.

Figure 21 shows the general diagram of the operation of

the AD7450 in this mode. The conversion is initiated on

the falling edge of

CS as described in the ‘Serial Interface

Section’.

To ensure the part remains fully powered up,

CS must remain low until at least 10 SCLK falling edges

have elapsed after the falling edge of

CS.

CS is brought high any time after the 10th SCLK fall-

ing edge, but before the 16th SCLK falling edge, the part

will remain powered up but the conversion will be termi-

nated and SDATA will go back into three-state.

Sixteen serial clock cycles are required to complete the

conversion and access the complete conversion result.

may idle high until the next conversion or may idle low

until sometime prior to the next conversion.

Once a data

transfer is complete, i.e. when SDATA has returned to

three-state, another conversion can be initiated after the

quiet time, tQUIET has elapsed by again bringing

CS low.

4 LEADING ZEROS + CONVERSION RESULT

SDATA

SCLK

Figure 21. Normal Mode Operation

Power Down Mode

This mode is intended for use in applications where

slower throughput rates are required; either the ADC is

powered down between each conversion, or a series of

conversions may be performed at a high throughput rate

and the ADC is then powered down for a relatively long

duration between these bursts of several conversions.

When the AD7450 is in the power down mode, all analog

circuitry is powered down.

To enter power down mode,

the conversion process must be interrupted by bringing

CS high anywhere after the second falling edge of SCLK

and before the tenth falling edge of SCLK as shown in

Figure 22.

Once

CS has been brought high in this window of

SCLKs, the part will enter power down and the conver-

sion that was initiated by the falling edge of

CS will be

terminated and SDATA will go back into three-state.

The time from the rising edge of

CS to SDATA three-

state enabled will never be greater than t8 (see the

‘Timing Specifications’).

CS is brought high before

the second SCLK falling edge, the part will remain in

normal mode and will not power-down.

This will avoid

accidental power-down due to glitches on the

CS line.

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