AD7450ARM datasheet(21/24 Pages) AD

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PRELIMINARY TECHNICAL DATA

–21–

AD7450

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7450 allows the part to be

directly connected to a range of different microproces-

sors. This section explains how to interface the AD7450

with some of the more common microcontroller and DSP

serial interface protocols.

AD7450 to ADSP21xx

The ADSP21xx family of DSPs are interfaced directly to

the AD7450 without any glue logic required.

The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data words

ISCLK = 1, Internal serial clock

TFSR = RFSR = 1, Frame every word

IRFS = 0,

ITFS = 1.

To implement the power-down mode SLEN should be

set to 1001 to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 25. The

ADSP21xx has the TFS and RFS of the SPORT tied

together, with TFS set as an output and RFS set as an

input. The DSP operates in Alternate Framing Mode and

the SPORT control register is set up as described. The

Frame Synchronisation signal generated on the TFS is

tied to

CS and as with all signal processing applications

equidistant sampling is necessary. However, in this ex-

ample, the timer interrupt is used to control the sampling

rate of the ADC and under certain conditions, equidistant

sampling may not be acheived.

AD7450*

SCLK

SDATA

SCLK

RFS

TFS

ADSP21xx*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 25. Interfacing to the ADSP 21xx

AD7450 to TMS320C5x/C54x

The serial interface on the TMS320C5x/C54x uses a

continuous serial clock and frame synchronization signals

to synchronize the data transfer operations with peripheral

devices like the AD7450. The

CS input allows easy

interfacing between the TMS320C5x/C54x and the

AD7450 without any glue logic required. The serial port

of the TMS320C5x/C54x is set up to operate in burst

mode with internal CLKX (TX serial clock) and FSX

(TX frame sync). The serial port control register (SPC)

must have the following setup: FO = 0, FSM = 1, MCM

= 1 and TXM = 1. The format bit, FO, may be set to 1

to set the word length to 8-bits, in order to implement the

power-down mode on the AD7450. The connection dia-

gram is shown in Figure 26. It should be noted that for

signal processing applications, it is imperative that the

frame synchronisation signal from the TMS320C5x/C54x

will provide equidistant sampling.

AD7450*

SCLK

SDATA

CLKX

FSR

TMS320C5x/C54x*

*ADDITIONAL PINS OMITTED FOR CLARITY

CLKR

FSX

Figure 26. Interfacing to the TMS320C5x/C54x

The timer registers etc., are loaded with a value which

will provide an interrupt at the required sample interval.

When an interrupt is received, a value is transmitted with

TFS/DT (ADC control word). The TFS is used to con-

trol the RFS and hence the reading of data. The frequency

of the serial clock is set in the SCLKDIV register. When

the instruction to transmit with TFS is given, (i.e.

AX0=TX0), the state of the SCLK is checked. The DSP

will wait until the SCLK has gone High, Low and High

before transmission will start. If the timer and SCLK val-

ues are chosen such that the instruction to transmit occurs

on or near the rising edge of SCLK, then the data may be

transmitted or it may wait until the next clock edge.

For example, the ADSP-2111 has a master clock fre-

quency

of 16MHz. If the SCLKDIV register is loaded

with the value 3 then a SCLK of 2MHz is obtained, and 8

master clock periods will elapse for every 1 SCLK period.

If the timer registers are loaded with the value 803, then

100.5 SCLKs will occur between interrupts and subse-

quently between transmit instructions. This situation will

result in non-equidistant sampling as the transmit instruc-

tion is occuring on a SCLK edge. If the number of

SCLKs between interrupts is a whole integer figure of N

then equidistant sampling will be implemented by the

DSP.

AD7450 to MC68HC16

The Serial Peripheral Interface (SPI) on the MC68HC16

is configured for Master Mode (MSTR = 1), Clock Polar-

ity Bit (CPOL) = 1 and the Clock Phase Bit (CPHA) = 0.

The SPI is configured by writing to the SPI Control Reg-

ister (SPCR) - see 68HC16 user manual. The serial

transfer will take place as a 16-bit operation when the

SIZE bit in the SPCR register is set to SIZE = 1. To

implement the power-down modes with an 8-bit transfer

set SIZE = 0. A connection diagram is shown in figure

27.

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