REV. PrJ

PRELIMINARY TECHNICAL DATA

–20–

AD7450

quired to change mode, then neither is a dummy cycle

required to place the track and hold into track.

POWER VERSUS THROUGHPUT RATE

By using the power-down mode on the AD7450 when not

converting, the average power consumption of the ADC

decreases at lower throughput rates.

Figure 24 shows

how, as the throughput rate is reduced, the device remains

in its power-down state longer and the average power con-

sumption reduces accordingly.

It shows this for both 5V

and 3V power supplies.

For example, if the AD7450 is operated in continous sam-

pling mode with a throughput rate of 100kSPS and an

SCLK of 18MHz and the device is placed in the power

down mode between conversions, then the power con-

sumption is calculated as follows:

Power dissipation during normal operation = 13mW max

If the power up time is 1 dummy cycle i.e. 1µsec, and the

remaining conversion time is another cycle i.e. 1µsec, then

the AD7450 can be said to dissipate 13mW for 2µsec*

during each conversion cycle.

If the throughput rate = 100kSPS then the cycle time =

10µsec and the average power dissipated during each cycle

is:

(2/10) x 13mW = 2.6mW

during normal operation is 6mW max.

The AD7450 can now be said to dissipate 6mW for 2µsec*

during each conversion cycle.

The average power dissipated during each cycle with a

throughput rate of 100kSPS is therefore:

(2/10) x 6mW = 1.2mW

This is how the power numbers in Figure 24 are calcu-

lated.

For throughput rates above 320kSPS, it is recommended

that for optimum power performance, the serial clock fre-

quency is reduced.

*This figure assumes a very small time used to enter the power down

mode. This will increase as the burst of clocks used to enter the power

down mode is increased.

0

50

100

150

200

250

300

350

TH ROU GH PU T (kSPS)

VDD = 5V

SCLK = 18M Hz

VDD = 3V

SCLK = 15M Hz

0.01

0.1

1

10

100

Figure 24. AD7450 Power versus Throughput Rate for

Power Down Mode