REV. 0

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a

AD9433

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2001

12-Bit, 105 MSPS/125 MSPS

IF Sampling A/D Converter

FUNCTIONAL BLOCK DIAGRAM

AIN

AIN

ENCODE

ENCODE

REF

OUT

REF

IN

GND

D11–D0

DFS

SFDR

12

12

PIPELINE

ADC

T/H

ENCODE

TIMING

REF

OUTPUT

STAGING

AD9433

FEATURES

IF Sampling up to 350 MHz

2 V p-p Analog Input Range Option

On-Chip Clock Duty Cycle Stabilization

On-Chip Reference and Track/Hold

SFDR Optimization Circuit

Excellent Linearity:

DNL =

0.25 LSB (Typ)

INL =

0.5 LSB (Typ)

750 MHz Full Power Analog Bandwidth

Power Dissipation = 1.35 W Typical @ 125 MSPS

Two’s Complement or Offset Binary Data Format

5.0 V Analog Supply Operation

2.5 V to 3.3 V TTL/CMOS Outputs

APPLICATIONS

Cellular Infrastructure Communication Systems

3G Single and Multicarrier Receivers

IF Sampling Schemes

Wideband Carrier Frequency Systems

Point to Point Radios

LMDS, Wireless Broadband

MMDS Base Station Units

Cable Reverse Path

Communications Test Equipment

Radar and Satellite Ground Systems

GENERAL INTRODUCTION

The AD9433 is a 12-bit monolithic sampling analog-to-digital

converter with an on-chip track-and-hold circuit and is designed

for ease of use. The product operates up to 125 MSPS conver-

sion rate and is optimized for outstanding dynamic performance

in wideband and high IF carrier systems.

The ADC requires a 5 V analog power supply and a differential

encode clock for full performance operation. No external refer-

ence or driver components are required for many applications.

The digital outputs are TTL/CMOS compatible and a separate

output power supply pin supports interfacing with 3.3 V or

2.5 V logic.

A user-selectable, on-chip proprietary circuit optimizes spurious-

free dynamic range (SFDR) versus signal-to-noise-and-distortion

(SINAD) ratio performance for different input signal frequencies,

providing as much as 83 dBc SFDR performance over the dc

to 70 MHz band.

The encode clock supports either differential or single-ended

input and is PECL-compatible. The output format is user-

selectable for binary or two’s complement and provides an

overrange (OR) signal.

Fabricated on an advanced BiCMOS process, the AD9433 is

available in a thermally enhanced 52-lead plastic quad flatpack

specified over the industrial temperature range (–40

°C to

+85

°C) and is pin-compatible with the AD9432.

PRODUCT HIGHLIGHTS

1. IF Sampling

The AD9433 maintains outstanding ac performance up to

input frequencies of 350 MHz. Suitable for 3G Wideband

Cellular IF sampling receivers.

2. Pin-Compatibility

This ADC has the same footprint and pin layout as the

AD9432, 12-Bit 80/105 MSPS ADC.

3. SFDR Performance

A user-selectable on-chip circuit optimizes SFDR performance

as much at 85 dBc from dc to 70 MHz.

4. Sampling Rate

At 125 MSPS, this ADC is ideally suited for current wireless

and wired broadband applications such as LMDS/MMDS

and cable reverse path.