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AD9433/PCB 数据表(PDF) 2 Page - Analog Devices |
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AD9433/PCB 数据表(HTML) 2 Page - Analog Devices |
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2 / 24 page  REV. 0 –2– ◊ AD9433–SPECIFICATIONS (VDD = 3.3 V, VCC = 5 V; internal reference; differential encode input, unless otherwise noted.) Test AD9433BSQ-105 AD9433BSQ-125 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Offset Error Full VI –5 0 +5 –5 0 +5 mV Gain Error 1 25 CI –7 1+3 –7 1+3 % FS Differential Nonlinearity (DNL) 2 25 C I –0.75 0.25 +0.75 –0.75 0.3 +0.75 LSB Full VI –1 +1 –1 +1 LSB Integral Nonlinearity (INL) 2 25 C I –1.0 0.5 +1.0 –1.0 0.5 +1.0 LSB Full VI –1.3 +1.3 –1.3 +1.3 LSB THERMAL DRIFT Offset Error Full V –50 –50 ppm/ C Gain Error1 Full V –125 –125 ppm/ C Reference Full V ±80 ±80 ppm/ C REFERENCE Internal Reference Volatge (VREFOUT) Full I 2.4 2.5 2.6 2.4 2.5 2.6 V Output Current (VREFOUT) Full V 100 100 µA Input Current (VREFIN) Full IV 50 50 µA ANALOG INPUTS Differential Input Voltage Range Full V 2.0 2.0 V ( AIN, AIN) Common-Mode Voltage Full V 4.0 4.0 V Input Resistance Full VI 2 3 4 2 3 4 k Ω Input Capacitance Full V 4 4 pF Analog Bandwidth, Full Power Full V 750 750 MHz POWER SUPPLY VCC Full IV 4.75 5.0 5.25 4.75 5.0 5.25 V VDD Full IV 2.7 3.3 2.7 3.3 V Power Dissipation 3 Full VI 1275 1425 1350 1500 mW Power Supply Rejection Ratio (PSRR) 25 CI 3 3 mV/V IVCC 2 Full VI 255 285 270 300 mA IVDD 2 Full VI 12.5 14 16 18 mA ENCODE INPUTS Internal Common-Mode Bias Full V 3.75 3.75 V Differential Input (ENC – ENC) Full V 500 500 mV Input Voltage Range Full IV –0.5 VCC + 0.05 –0.5 VCC + 0.05 V Input Common-Mode Range Full IV 2.0 4.25 2.0 4.25 V Input Resistance Full VI 6 6 k Ω Input Capacitance 25 CV 3 3 pF DIGITAL INPUTS Input High Voltage Full I 2.0 2.0 V Input Low Voltage Full I 0.8 0.8 V Input High Current (VIN = 5 V) Full V 50 50 µA Input Low Current (VIN = 0 V) Full V 50 50 µA DIGITAL OUTPUTS Logic “1” Voltage Full VI VDD – 0.05 VDD – 0.05 V Logic “0” Voltage Full VI 0.05 0.05 V Output Coding Two’s Complement or Offset Binary NOTES 1Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input). 2SFDR disabled (SFDR = GND) for DNL and INL specifications. 3Power dissipation measured with rated encode and a dc analog input (Outputs Static, I VDD = 0). IVCC and IVDD measured with 10.3 MHz analog input @ –0.5 dBFS. Specifications subject to change without notice. DC SPECIFICATIONS |
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