REV. 0

AD9433

–13–

APPLICATION NOTES

Theory of Operation

The AD9433 is a multibit pipeline converter that uses a switched

capacitor architecture. Optimized for high speed, this converter

provides flat dynamic performance up to and beyond the Nyquist

limit. DNL transitional errors are calibrated at final test to a

typical accuracy of 0.25 LSB or less.

USING THE AD9433

ENCODE Input

Any high-speed A/D converter is extremely sensitive to the quality

of the sampling clock provided by the user. A track/hold circuit

is essentially a mixer, and any noise, distortion, or timing jitter

on the clock will be combined with the desired signal at the A/D

output. For that reason, considerable care has been taken in the

design of the ENCODE input of the AD9433, and the user is

advised to give commensurate thought to the clock source.

The AD9433 has an internal clock duty cycle stabilization

circuit that locks to the rising edge of ENCODE (falling edge

of

ENCODE if driven differentially), and optimizes timing

internally. This allows for a wide range of input duty cycles at

the input without degrading performance. Jitter in the rising

edge of the input is still of paramount concern, and is not

reduced by the internal stabilization circuit. This circuit is

always on, and cannot be disabled by the user.

The ENCODE and

ENCODE inputs are internally biased to

3.75 V (nominal), and support either differential or single-

ended signals. For best dynamic performance, a differential

signal is recommended. Good performance is obtained using

an MC10EL16 in the circuit to directly drive the encode

inputs, as illustrated in Figure 7.

FREQUENCY – MHz

–120

0

11.52

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

23.04

34.56

46.08

70.0 MHz, SFDR Enabled

ENCODE

ENCODE

PECL

GATE

510

510

AD9433

Figure 7. Using PECL to Drive the

ENCODE Inputs

Often, the cleanest clock source is a crystal oscillator producing

a pure, single-ended sine wave. In this configuration, or with

any roughly symmetrical, single-ended clock source, the signal

can be ac-coupled to the ENCODE input. To minimize jitter,

the signal amplitude should be maximized within the input

range described in Table I below. The 12 k

Ω resistors to

ground at each of the inputs, in parallel with the internal bias

resistors, set the common-mode voltage to approximately 2.5 V,

allowing the maximum swing at the input. The

ENCODE input

should be bypassed with a capacitor to ground to reduce noise.

This ensures that the internal bias voltage is centered on the

encode signal. For best dynamic performance, impedances at

ENCODE and

ENCODE should match.

ENCODE

ENCODE

AD9433

50

25

12k

12k

0.1 F

0.1 F

50

SINE

SOURCE

Figure 8. Single-Ended Sine Source Encode Circuit

FREQUENCY – MHz

–120

0

9.6

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

19.2

28.8

38.4

Carriers, Differential AIN, SFDR Enabled