REV. 0

AD9433

–14–

Shown in Figure 9 is another preferred method for clocking the

AD9433. The clock source (low jitter) is converted from single-

ended to differential using an RF transformer. The back-to-back

Schottky diodes across the transformer secondary limit clock

excursions into the AD9433 to approximately 0.8 V p-p differ-

ential. This helps prevent the large voltage swings of the clock

from feeding through to the other portions of the AD9433, and

limits the noise presented to the ENCODE inputs. A crystal

clock oscillator can also be used to drive the RF transformer if

an appropriate limiting resistor (typically 100

Ω) is placed in the

series with the primary.

ENCODE

ENCODE

AD9433

CLOCK

SOURCE

0.1 F

100

HMS2812

DIODES

T1–4T

Figure 9. Transformer-Coupled Encode Circuit

ENCODE Voltage Level Definition

The voltage level definitions for driving ENCODE and

ENCODE in single-ended and differential mode are shown

in Figure 10.

Table I. ENCODE Inputs

Description

Minimum Nominal Maximum

Differential Signal Amplitude 200 mV

750 mV

5.5 V

Input Voltage Range

–0.5 V

Internal Common-Mode Bias

3.750 V

External Common-Mode Bias 2.0 V

4.25 V

0.1 F

ENCODE

ENCODE

ENCODE

ENCODE

Figure 10. Differential and Single-Ended Input Levels

Analog Input

The analog input to the AD9433 is a differential buffer.

The input buffer is self-biased by an on-chip resistor divider

that nominally sets the dc common-mode voltage to 4 V (see

Equivalent Circuits section). Rated performance is achieved

by driving the input differentially. Minimum input offset voltage

is obtained when driving from a source with a low differential

source impedance, such as a transformer, in ac applica-

tions (See Figure 11). Capacitive coupling at the inputs will

increase the input offset voltage by as much as 50 mV.

50

ANALOG

SIGNAL

SOURCE

1:1

25

25

AIN

AIN

0.1 F

Figure 11. Transformer-Coupled Analog Input Circuit

In the highest frequency applications, two transformers con-

nected in series may be necessary to minimize even-order

harmonic distortion. The first transformer will isolate and con-

vert the signal to a differential signal, but the grounded input on

the primary side will degrade amplitude balance on the second-

ary winding. Capacitive coupling between the windings causes

this imbalance. Since one input to the first transformer is

grounded, there is little or no capacitive coupling, resulting in an

amplitude mismatch at the first transformers output. A second

transformer will improve the amplitude balance, and thus

improve the harmonic distortion. A wideband transformer, such

as the ADT1-1WT from Mini Circuits, is recommended for

these applications, as the bandwidth through the two transformers

will be reduced by the

√2.

50

ANALOG

SIGNAL

SOURCE

1:1

25

25

AIN

AIN

0.1 F

1:1

AD9433

Figure 12. Driving the Analog Input with Two Transformers

for Improved Even-Order Harmonics

Driving the ADC single-endedly will degrade performance,

particularly even-order harmonics. For best dynamic performance,

impedances at AIN and

AIN should match.

Special care was taken in the design of the analog input section

of the AD9433 to prevent damage and corruption of data when

the input is overdriven.

SFDR Optimization

The SFDR MODE pin enables (SFDR MODE = 1) a propri-

etary circuit that may improve the spurious free dynamic range

(SFDR) performance of the AD9433. It is useful in applications

where the dynamic range of the system is limited by discrete

spurious frequency content caused by nonlinearities in the ADC

transfer function.

Enabling this circuit will give the circuit a dynamic transfer

function, meaning that the voltage threshold between two

adjacent output codes may change from clock cycle to clock

cycle. While improving spurious frequency content, this

dynamic aspect of the transfer function may be inappropriate

for some time domain applications of the converter. Connecting

the SFDR MODE pin to ground will disable this function. The

typical performance curves section of the data sheet illustrates

the improvement in the linearity of the converter and its effect

on spurious free dynamic range (TPC 1, 2, 15, 18).