AD9857

–5–

REV. 0

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

I/O

Pin Function

20–14, 7–1

D0–D6, D7–D13

I

14-Bit Parallel Data Bus for I and Q Data. The required numeric format is two’s

complement with D13 as the sign bit and D12–D0 as the magnitude bits.

Alternating 14-bit words are demultiplexed onto the I and Q data pathways

(except when operating in the Interpolating DAC Mode, in which case every

word is routed onto the I data path). When the TxENABLE pin is asserted high,

the next accepted word is presumed to be I data, the next Q data, and so forth.

8–10, 31–33, 73–75

DVDD

3.3 V Digital Power Pin(s).

11–13, 28–30, 70–72,

76–78

DGND

Digital Ground Pin(s).

21

PS1

I

Profile Select Pin 1. The LSB of the two profile select pins. In conjunction

with PS0, selects one of four profile configurations.

22

PS0

I

Profile Select Pin 0. The MSB of the two profile select pins. In conjunction

with P1, selects one of four profile configurations.

23

CS

I

Serial Port Chip Select Pin. An active low signal that allows multiple devices

to operate on a single serial bus.

24

SCLK

I

Serial Port Data Clock Pin. The serial data CLOCK for the Serial Port.

25

SDIO

I/O

Serial Port Input/Output Data Pin. Bidirectional serial DATA pin for the Serial

Port. This pin can be programmed to operate as a serial input only pin, via a

control register bit 00h<7>. The default state is bidirectional.

26

SDO

O

Serial Port Output Data Pin. This pin serves as the serial data output pin when the

SDIO pin is configured for serial input only mode. The default state is three-state.

27

SYNCIO

I

Serial Port Synchronization Pin. Synchronizes the serial port without affecting

the programmable register contents. This is an active high input that aborts

the current serial communication cycle.

34, 41, 51, 52, 57

NC

No Connect.

35, 37, 38, 43, 48,

54, 58, 64

AVDD

3.3 V Analog Power Pin(s).

36, 39, 40, 42, 44, 47,

53, 56, 59, 61, 65

AGND

Analog Ground Pin(s).

45

IOUT

O

DAC Output Pin. Normal DAC output current (analog).

46

IOUT

O

DAC Complementary Output Pin. Complementary DAC output current (analog).

49

DAC_BP

DAC Reference Bypass. Normally not used.

50

DAC_RSET

I

DAC Current Set Pin. Sets DAC reference current

55

PLL_FILTER

O

PLL Filter. R-C network for PLL Filter.

60

DIFFCLKEN

I

Clock Mode Select Pin. A logic high on this pin selects DIFFERENTIAL

REFCLK input mode. A logic low selects the SINGLE-ENDED REFCLK

input mode.

62

REFCLK

I

Reference Clock Pin. In single-ended Clock Mode, this pin is the Reference

Clock input. In differential Clock Mode, this pin is the positive clock input.

63

REFCLK

I

Inverted Reference Clock Pin. In differential Clock Mode, this pin is the

negative clock input.

66

DPD

I

Digital Power-Down Pin. Assertion of this pin shuts down the digital sections of

the device to conserve power. However, if selected, the PLL remains operational.

67

RESET

I

Hardware RESET Pin. An active high input that forces the device into a

predefined state.

68

PLL_LOCK

O

PLL Lock Pin. Active high output signifying, in real time, when PLL is in

“lock” state.

69

CIC_OVRFL

O

CIC Overflow Pin. Activity on this pin indicates that the CIC filters are in

“overflow” state. This pin is normally “low” unless a CIC overflow occurs.

79

PDCLK/FUD

I/O

Parallel Data Clock/Frequency Update Pin. When not in Single-Tone Mode, this

pin is an output signal that should be used as a clock to synchronize the acceptance

of the 14-bit parallel data words on Pins D13–D0. In Single-Tone Mode, this pin is

an input signal that synchronizes the transfer of a changed frequency tuning word

(FTW) in the active profile (PSx) to the accumulator (FUD = Frequency Update

signal). When profiles are changed by means of the PS–PS1 pins, the FUD does

not have to be asserted to make the FTW active.

80

TxENABLE

I

When TxENABLE is asserted, the device processes the data through the I and Q

data pathways; otherwise 0s are internally substituted for the I and Q data entering

the signal path. The first data word accepted when the TxENABLE is asserted

high is treated as I data, the next data word is Q data, and so forth.

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