AD9857SLASHPCB datasheet(13/31 Pages) AD

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AD9857

–13–

REV. 0

TDH

TDS

TDH

TxENABLE

PDCLK

D<13:0>

Figure 19. 14-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode

TDH

IK–1

TDS

TDH

TxENABLE

PDCLK

D<13:0>

TDS IS THE DATA SETUP TIME

TDH IS THE DATA HOLD TIME

Figure 20. 14-Bit Parallel Port Timing Diagram—Interpolating DAC Mode

(see the Proﬁle section) to be transferred to the accumulator of

the DDS, thus starting the frequency synthesis process.

After loading the frequency tuning word to a proﬁle, a FUD signal

is not needed when switching between proﬁles using the two proﬁle

select pins (PS0, PS1). When switching between proﬁles, the fre-

quency tuning word in the proﬁle register is becomes effective.

In the Quadrature Modulation mode the PDCLK rate is twice

the rate of the I (or Q) data rate. The AD9857 expects interleaved

I and Q data words at the parallel port with one word per PDCLK

rising edge. One I word and one Q word together comprise one

internal sample. Each sample is propagated along the internal

data pathway in parallel.

In the Interpolating DAC mode, however, the PDCLK rate is

the same as the “I” data rate since the “Q” data path is inactive.

In this mode, each PDCLK rising edge latches a data word into

the “I” data path.

The PDCLK is provided as a continuous clock (i.e., always

active). However, the assertion of PDCLK may be optionally

qualiﬁed internally by the PLL Lock Indicator if the user elects to

set the PLL Lock Control bit in the appropriate Control Register.

Data supplied by the user to the 14-bit Parallel Port is latched

into the device coincident with the rising edge of the PDCLK.

In the Quadrature Modulation Mode the rising edge of the

TxENABLE signal is used to synchronize the device. While

TxENABLE is in the Logic 0 state, the device ignores the 14-bit

data applied to the parallel port and allows the internal data path to

be flushed by forcing 0s down the I and Q data pathway. On the

rising edge of TxENABLE the device is ready for the ﬁrst “I”

word. The ﬁrst “I” word is latched into the device coincident with

the rising edge of PDCLK. The next rising edge of PDCLK

latches in a “Q” word, etc., until TxENABLE is set to a Logic 0

state by the user.

When in the Quadrature Modulation Mode it is important that

the user ensure that an even number of PDCLK intervals are

observed during any given TxENABLE period. This is because

the device must capture both an I and a Q value before the data

can be processed along the internal data pathway.

The timing relationship between TxENABLE, PDCLK, and

DATA is shown in Figures 19 and 20.

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