–3–

AD9857

REV. 0

Test

AD9857

Parameter

Temp

Level

Min

Typ

Max

Unit

SPURIOUS POWER (Off Channel, Measured in

Equivalent Bandwidth), Output Attenuated 18 dB

Relative to Full Scale

6.4 MHz Bandwidth

25

°C

IV

–51

dBc

3.2 MHz Bandwidth

25

°C

IV

–54

dBc

1.6 MHz Bandwidth

25

°C

IV

–56

dBc

0.8 MHz Bandwidth

25

°C

IV

–59

dBc

0.4 MHz Bandwidth

25

°C

IV

–62

dBc

0.2 MHz Bandwidth

25

°C

IV

–63

dBc

TIMING CHARACTERISTICS

Serial Control Bus

Maximum Frequency

25

°C

I

10

MHz

°CI

30

ns

°CI

30

ns

Maximum Clock Rise/Fall Time

25

°CI

1

ms

°CI

30

ns

°CI

0

ns

°CI

35

ns

Wake-Up Time

1

25

°CI

1

ms

°C

I

5

Minimum

CS Setup Time

25

°CI

40

ns

CMOS LOGIC INPUTS

Logic “1” Voltage

25

°C

I

2.0

V

Logic “0” Voltage

25

°C

I

0.8

V

Logic “1” Current

25

°CI

5

µA

Logic “0” Current

25

°CI

5

µA

Input Capacitance

25

°CV

3

pF

CMOS LOGIC OUTPUTS (1 mA LOAD)

Logic “1” Voltage

25

°C

I

2.7

mA

Logic “0” Voltage

25

°C

I

0.4

mA

°C, REFCLK = 200 MHz)

Full Operating Conditions

25

°C

I

615

mA

160 MHz Clock (

×16)

25

°C

I

515

mA

120 MHz Clock (

×12)

25

°C

I

400

mA

Burst Operation (25%)

25

°C

I

450

mA

Single-Tone Mode

25

°C

I

310

mA

Power-Down Mode

25

°CI

80

mA

Full-Sleep Mode

25

°C

I

13.5

mA

NOTES

Wake-Up Time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the Reference Clock Multi-

plier lock can be determined by observing the signal on the PLL_LOCK pin.

SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor. If the Reference Clock Multiplier is not

used, the SYSCLK frequency is the same as the external REFCLK frequency.

Specifications subject to change without notice.