AD9857SLASHPCB datasheet(16/31 Pages) AD

16 / 31 page

AD9857

–16–

REV. 0

The transfer function of the CIC Interpolating Filter is:

jf k

()

– (

= ∑









×× ×

−

where R is the interpolation rate, and f is the frequency relative

to SYSCLK.

Quadrature Modulator

The digital quadrature modulator stage is used to frequency shift

the baseband spectrum of the incoming data stream up to the

desired carrier frequency (this process is known as upconversion).

It should be noted that at this point the incoming data has been

converted from an incoming sampling rate of fIN to an I/Q sam-

pling rate equal to SYSCLK. The purpose of the upsampling

process is to make the data sampling rate equal to the sampling

rate of the carrier signal.

The carrier frequency is controlled numerically by a Direct Digital

Synthesizer (DDS). The DDS uses the internal reference clock

(SYSCLK) to generate the desired carrier frequency with a high

degree of precision. The carrier is applied to the I and Q multi-

pliers in quadrature fashion (90

° phase offset) and summed to yield

a data stream that represents the quadrature modulated carrier.

A key point is that the modulation is done digitally which elimi-

nates the phase and gain imbalance and crosstalk issues typically

associated with analog modulators. Note that the modulated

“signal” is actually a number stream sampled at the rate of

SYSCLK, the same rate at which the output D/A converter is

clocked.

The quadrature modulator operation is also controlled by spectral

invert bits in each of the four proﬁles. The quadrature modu-

lation takes the form:

× COS(ω) + Q × SIN(ω) when the spectral invert bit is set to a

Logic 1.

× COS(ω) – Q × SIN(ω) when the spectral invert bit is set

to a Logic 0.

DDS Core

The direct digital synthesizer (DDS) block generates the sin/cos

carrier reference signals that digitally modulate the I/Q data

paths. The DDS frequency is tuned via the serial control port

with a 32-bit tuning word (per profile). This allows the AD9857’s

output carrier frequency to be very precisely tuned while still

providing output frequency agility.

The equation relating output frequency (fOUT) of the AD9857

digital modulator to the frequency tuning word (FTWORD)

and the system clock (SYSCLK) is:

fOUT = (FTWORD

× SYSCLK)/232

where fOUT and SYSCLK frequencies are in Hz and FTWORD is

a decimal number from 0 to 2,147,483,647 (2

31–1)

Example: Find the FTWORD for fOUT = 41 MHz and SYSCLK =

122.88 MHz

If fOUT = 41 MHz and SYSCLK = 122.88 MHz, then

FTWORD = 556AAAAB hex

Loading 556AAAABh into control bus registers 08h–0Bh (for

Proﬁle 1) programs the AD9857 for fOUT = 41 MHz, given a

SYSCLK frequency of 122.88 MHz.

Inverse SINC Filter

The sampled carrier data stream is the input to the digital-to-

analog converter (DAC) integrated onto the AD9857. The DAC

output spectrum is shaped by the characteristic sin(x)/x (or

SINC) envelope, due to the intrinsic zero-order hold effect asso-

ciated with DAC-generated signals. Since the shape of the SINC

envelope is well known, it can be compensated for. This envelope

restoration function is provided by the optional inverse SINC

ﬁlter preceding the DAC. This function is implemented as an

FIR ﬁlter, which has a transfer function that is the exact inverse of

the SINC response. When the Inverse SINC Filter is selected, it

modiﬁes the incoming data stream so that the desired carrier

envelope, which would otherwise be shaped by the SINC envelope,

is restored. It should be noted, however, that this correction is

only complete for carrier frequencies up to approximately 45%

of SYSCLK.

It should be noted that the inverse SINC filter introduces about a

3.5 dB loss at low frequencies as compared to the gain with the

inverse SINC filter turned off. This is done to flatten the overall

gain from dc to 45% of SYSCLK.

The inverse SINC ﬁlter can be bypassed if it is not needed. If the

inverse SINC ﬁlter is bypassed, its clock is stopped, thus reducing

the power dissipation of the part.

Output Scale Multiplier

An 8-bit multiplier (Output Scale Value in the block diagram) pre-

ceding the DAC provides the user with a means of adjusting the

ﬁnal output level. The multiplier value is programmed via the

appropriate control registers, per each proﬁle. The LSB weight

is 2

–7, which yields a multiplier range of 0 to 1.9921875, or

nearly 2

×. Since the quadrature modulator has an intrinsic loss

of 3 dB (1/

√2), programming the multiplier for a value of

√2) will restore the data to the full-scale range of the DAC when

the device is operating in the Quadrature Modulation Mode. Since

the AD9857 defaults to the Modulation Mode, the default value

for the multiplier is B5h (which corresponds to

√2).

Programming the output scale multiplier to unity gain (80h) by-

passes the stage, reducing power dissipation.

14-Bit D/A Converter

A 14-bit digital-to-analog converter (DAC) is used to convert the

digitally processed waveform into an analog signal. The worst-case

spurious signals due to the DAC are the harmonics of the funda-

mental signal and their aliases (please see Analog Devices, DDS

Tutorial at http://www.analog.com/dds for a detailed explanation

of aliases). The wideband 14-bit DAC in the AD9857 maintains

spurious-free dynamic range (SFDR) performance of –60 dBc

up to AOUT = 42 MHz and –55 dBc up to AOUT = 65 MHz.

The conversion process will produce aliased components of the

fundamental signal at n

SYSCLK

± FCARRIER (n = 1, 2, 3).

These are typically ﬁltered with an external RLC ﬁlter at the DAC

output. It is important for this analog ﬁlter to have a sufﬁciently

flat gain and linear phase response across the bandwidth of

interest to avoid modulation impairments.

AD9857/PCB 数据表(PDF) 16 Page - Analog Devices

AD9857/PCB 数据表(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

数据表下载