AD9857SLASHPCB datasheet(20/31 Pages) AD

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AD9857

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MSB/LSB Transfers

The AD9857 serial port can support both most signiﬁcant bit

(MSB) ﬁrst or least signiﬁcant bit (LSB) ﬁrst data formats. This

functionality is controlled by the Control Register 00h<6> bit.

The default value of Control Register 00h<6> is low (MSB ﬁrst).

When Control Register 00h<6> is set high, the AD9857 serial

port is in LSB ﬁrst format. The instruction byte must be written

in the format indicated by Control Register 00h<6>. That is, if

the AD9857 is in LSB ﬁrst mode, the instruction byte must be

written from least signiﬁcant bit to most signiﬁcant bit.

Multibyte data transfers in MSB format can be completed by

writing an instruction byte that includes the register address of

the most signiﬁcant byte. In MSB ﬁrst mode, the serial port in-

ternal byte address generator decrements for each byte required

of the multibyte communication cycle. Multibyte data transfers

in LSB ﬁrst format can be completed by writing an instruction

byte that includes the register address of the least signiﬁcant

byte. In LSB ﬁrst mode, the serial port internal byte address

generator increments for each byte required of the multibyte

communication cycle.

Notes on Serial Port Operation

The AD9857 serial port conﬁguration bits reside in Bits 6 and 7

of register address 0h. It is important to note that the conﬁguration

changes immediately upon writing to this register. For multibyte

transfers, writing to this register may occur during the middle of

a communication cycle. Care must be taken to compensate for this

new conﬁguration for the remainder of the current communica-

tion cycle.

The AD9857 serial port controller address will roll from 19h to

0h for multibyte I/O operations if the MSB ﬁrst mode is active.

The serial port controller address will roll from 0h to 19h for

multibyte I/O operations if the LSB ﬁrst mode is active.

The system must maintain synchronization with the AD9857 or

the internal control logic will not be able to recognize further

instructions. For example, if the system sends an instruction

byte for a 2-byte write, then pulses the SCLK pin for a 3-byte

write (24 additional SCLK rising edges), communication syn-

chronization is lost. In this case, the ﬁrst 16 SCLK rising edges

after the instruction cycle will properly write the ﬁrst two data

bytes into the AD9857, but the next eight rising SCLK edges are

interpreted as the next instruction byte, not the ﬁnal byte of the

previous communication cycle.

In the case where synchronization is lost between the system and

the AD9857, the SYNC I/O pin provides a means to re-establish

synchronization without reinitializing the entire chip. The SYNC

I/O pin enables the user to reset the AD9857 state machine to

accept the next eight SCLK rising edges to be coincident with

the instruction phase of a new communication cycle. By apply-

ing and removing a “high” signal to the SYNC I/O pin, the

AD9857 is set to once again begin performing the communica-

tion cycle in synchronization with the system. Any information

that had been written to the AD9857 registers during a valid

communication cycle prior to loss of synchronization will

remain intact.

Instruction Byte

The instruction byte contains the following information as shown

in Table II.

Table II. Instruction Byte Information

MSB

LSB

W—Bit 7 of the instruction byte determines whether a read or

write data transfer will occur after the instruction byte write.

Logic high indicates read operation. Logic zero indicates a write

operation.

N1, N0—Bits 6 and 5 of the instruction byte determine the

number of bytes to be transferred during the data transfer cycle

of the communications cycle. The bit decodes are shown in

Table III.

Table III. N1, N2 Decode Bits

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte

determine which register is accessed during the data transfer

portion of the communications cycle. For multibyte transfers,

this address is the starting byte address. The remaining register

addresses are generated by the AD9857.

SERIAL INTERFACE PORT PIN DESCRIPTION

SCLK—Serial Clock. The serial clock pin is used to synchro-

nize data to and from the AD9857 and to run the internal state

machines. SCLK maximum frequency is 10 MHz.

CS—Chip Select. Active low input that allows more than one

device on the same serial communications lines. The SDO and

SDIO pins will go to a high-impedance state when this input is

high. If driven high during any communications cycle, that cycle is

suspended until

CS is reactivated low. Chip Select can be tied

low in systems that maintain control of SCLK.

SDIO—Serial Data I/O. Data is always written into the AD9857

on this pin. However, this pin can be used as a bidirectional

data line. The conﬁguration of this pin is controlled by Bit 7 of

the SDIO pin as bidirectional.

SDO—Serial Data Out. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In the

case where the AD9857 operates in a single bidirectional I/O

mode, this pin does not output data and is set to a high-impedance

state.

SYNCIO—Synchronizes the I/O port state machines without

affecting the addressable registers contents. An active high input

on the SYNC I/O pin causes the current communication cycle to

abort. After SYNC I/O returns low (Logic 0) another communi-

cation cycle may begin, starting with the instruction byte write.

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