AD9857SLASHPCB datasheet(21/31 Pages) AD

21 / 31 page

AD9857

–21–

REV. 0

CONTROL REGISTER DESCRIPTION

Reference Clock (REFCLK) Multiplier—Register Address 00h,

Bits 0, 1, 2, 3, 4

A 5-bit number (M), the value of which determines the multipli-

cation factor for the internal PLL (Bit 4 is the MSB). The system

clock (SYSCLK) is M times the frequency of the REFCLK input

signal. If M = 01h, the PLL circuit is bypassed and fSYSCLK =

fREFCLK. If 04h

≤ M ≤ 14h, the PLL multiplies the REFCLK fre-

quency by M (4–20 decimal). Any other value of M is considered

an invalid entry.

PLL Lock Control—Register Address 00h, Bit 5

When set to a logic 0, the device uses the status of the PLL

Lock Indicator pin to internally control the operation of the 14-

bit parallel data path. When set to a Logic 1, the internal control

logic ignores the status of the PLL Lock Indicator pin.

LSB First—Register Address 00h, Bit 6

When set to a Logic 1, the serial interface accepts serial data

in LSB First format. When set to a Logic 0, MSB First for-

mat is assumed.

SDIO Input Only—Register Address 00h, Bit 7

When set to a Logic 1, the serial data I/O pin (SDIO) is config-

ured as an input only pin. When set to a logic 0, the SDIO pin

has bidirectional operation.

Operating Mode—Register Address 01h, Bits 0, 1

00h: Selects the Quadrature Modulation Mode of operation.

01h: Selects the Single-Tone Mode of operation.

02h: Selects the Interpolating DAC Mode of operation.

03h: Invalid entry.

Auto Power-Down—Register Address 01h, Bit 2

When set to a Logic 1, the device automatically switches into its

low-power mode whenever TxENABLE is deasserted for a suffi-

ciently long period of time. When set to a Logic 0, the device

only powers down in response to the Digital Power-Down pin.

Full Sleep Mode—Register Address 01h, Bit 3

When set to a Logic 1, the device completely shuts down.

Reserved—Register Address 01h, Bit 4

Reserved—Register Address 01h, Bit 5

This bit must always be set to 0.

Inverse SINC Bypass—Register Address 01h, Bit 6

When set to a Logic 1, the Inverse Sinc filter is BYPASSED.

When set to a Logic 0, the Inverse Sinc filter is active.

CIC Clear—Register Address 01h, Bit 7

When set to a Logic 1, the CIC filters are cleared. When set to a

Logic 0, the CIC filters operate normally.

PROFILE #0

Tuning Word—Register Address 02h, Bits 0, 1, 2, 3, 4, 5, 6, 7

The lower byte of the 32-bit frequency tuning word, Bits 0–7.

Tuning Word—Register Address 03h, Bits 0, 1, 2, 3, 4, 5, 6, 7

The second byte of the 32-bit frequency tuning word, Bits 8–15.

Tuning Word—Register Address 04h, Bits 0,1, 2, 3, 4, 5, 6, 7

The third byte of the 32-bit frequency tuning word, Bits 16–23.

Tuning Word—Register Address 05h, Bits 0, 1, 2, 3, 4, 5, 6, 7

The fourth byte of the 32-bit frequency tuning word, Bits 24–31.

Inverse CIC Bypass—Register Address 06h, Bit 0

When set to a Logic 1, the Inverse CIC filter is BYPASSED.

When set to a Logic 0, the Inverse CIC filter is active.

Spectral Invert—Register Address 06h, Bit 1

The quadrature modulator takes the form:

× cos(ω) + Q × sin(ω) when set to a Logic 1.

× cos(ω) – Q × sin(ω) when set to a Logic 0.

CIC Interpolation Rate—Register Address 06h, Bits 2, 3, 4,

5, 6, 7

00h: Invalid entry.

01h: CIC filters BYPASSED.

02h–3Fh: CIC interpolation rate (2–63, decimal).

Output Scale Factor—Register Address 07h, Bits 0, 1, 2, 3, 4,

5, 6, 7

An 8-bit number that serves as a multiplier for the data pathway

before the data is delivered the DAC. It has an LSB weight of 2

–7

(0.0078125). This yields a multiplier range of 0 to 1.9921875.

PROFILE #1

Tuning Word—Register Address 08h, Bits 0, 1, 2, 3, 4, 5, 6, 7

The lower byte of the 32-bit frequency tuning word, Bits 0–7.

Tuning Word—Register Address 09h, Bits 0, 1, 2, 3, 4, 5, 6, 7

The second byte of the 32-bit frequency tuning word, Bits 8–15.

Tuning Word—Register Address 0Ah, Bits 0, 1, 2, 3, 4, 5, 6, 7

The third byte of the 32-bit frequency tuning word, Bits 16–23.

Tuning Word—Register Address 0Bh, Bits 0, 1, 2, 3, 4, 5, 6, 7

The fourth byte of the 32-bit frequency tuning word, Bits 24–31.

Inverse CIC Bypass—Register Address 0Ch, Bit 0

When set to a Logic 1, the Inverse CIC filter is BYPASSED.

When set to a Logic 0, the Inverse CIC filter is active.

Spectral Invert—Register Address 0Ch, Bit 1

The quadrature modulator takes the form:

× cos(ω) + Q × sin(ω) when set to a Logic 1.

× cos(ω) + Q × sin(ω) when set to a Logic 0.

CIC Interpolation Rate—Register Address 0Ch, Bits 2, 3, 4,

5, 6, 7

00h: Invalid entry.

01h: CIC filters BYPASSED.

02h–3Fh: CIC interpolation rate (2–63, decimal).

Output Scale Factor—Register Address 0Dh, Bits 0, 1, 2, 3, 4,

5, 6, 7

An 8-bit number that serves as a multiplier for the data pathway

before the data is delivered the DAC. It has an LSB weight of 2

–7

(0.0078125). This yields a multiplier range of 0 to 1.9921875.

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