AD9857SLASHPCB datasheet(11/31 Pages) AD

11 / 31 page

AD9857

–11–

REV. 0

Single-Tone Mode

A block diagram of the AD9857 operating in the Single-Tone

Mode is shown in Figure 17. In the Single-Tone Mode both the

I and Q data paths are disabled from the 14-bit Parallel Data

Port up to and including the modulator. The PDCLK/FUD

pin is an input and functions as a Frequency Update (FUD)

control signal. This is necessary because the frequency tuning

word is programmed via the asynchronous serial port. The FUD

signal causes the new frequency tuning word to become active.

In Single-Tone Mode, the cosine portion of the DDS serves as

the signal source. The output signal consists of a single frequency

as determined by the tuning word stored in the appropriate control

In the Single-Tone Mode, no 14-bit parallel data is applied to the

AD9857. The internal DDS core is used to produce a single fre-

quency signal according to the tuning word. The single-tone signal

then moves toward the output, where the Inverse SINC ﬁlter and

the output scaling can be applied. Finally, the digital single-tone

signal is converted to the analog domain by the 14-bit DAC.

PDCLK/

FUD

INVERSE

SINC FILTER

INV

SINC

14-BIT

DAC

DAC_RSET

IOUT

OUTPUT

SCALE

VALUE

TUNING

WORD

TIMING & CONTROL

DDS

CORE

REFCLK

MODE

CONTROL

CLOCK

MULTIPLIER

– 20 )

PROFILE

SELECT

LOGIC

POWER-

DOWN

LOGIC

CONTROL REGISTERS

RESET

SERIAL

PORT

DIGITAL

POWER-

DOWN

PS1

PLL

LOCK

PS0

CLOCK

INPUT

MODE

AD9857

Figure 17. Single-Tone Mode

AD9857/PCB 数据表(PDF) 11 Page - Analog Devices

AD9857/PCB 数据表(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

数据表下载