ADMC331BST datasheet(12/36 Pages) AD

12 / 36 page

ADMC331

–12–

REV. B

Boot Loading

On power-up or reset, the ADMC331 is configured so that

execution begins at the internal PM ROM at address 0x0800.

This starts execution of the internal monitor function that first

performs some initialization functions and copies a default inter-

rupt vector table to addresses 0x0000–0x002F of program memory

RAM. The monitor next attempts to boot load from an external

SROM or E

2PROM on SPORT1 using the three wire connec-

tion of Figure 4. The monitor program first toggles the RFS1/

SROM pin of the ADMC331 to reset the serial memory device.

If an SROM or E

2PROM is connected to SPORT1, data is

clocked into the ADMC331 at a rate CLKOUT/20. Both pro-

gram and data memory RAM can be loaded from the SROM or

2PROM. After the boot load is complete, program execution

begins at address 0x0030. This is where the first instruction of

the user code should be placed.

If boot loading from an E

2PROM is unsuccessful, the monitor

code reconfigures SPORT1 as a UART and attempts to receive

commands from an external device on this serial port. The

monitor then waits for a byte to be received over SPORT1,

locks onto the baud rate of the external device (autobaud fea-

ture) and takes in a header word that tells it with what type of

device it is communicating. There are six alternatives:

• A UART boot loader such as a Motorola 68HC11SCI port.

• A synchronous slave boot loader (the clock is external).

• A synchronous master boot loader (the ADMC331 provides the

clock).

• A UART debugger interface.

• A synchronous master debugger interface.

• A synchronous slave debugger interface.

With the debugger interface, the monitor enters an interactive

mode in which it processes commands received from the exter-

nal device.

DSP Control Registers

The DSP core has a system control register, SYSCNTL, memory

mapped at DM (0x3FFF). SPORT0 is enabled when Bit 12 is

set, disabled when this bit is cleared. SPORT1 is enabled when

Bit 11 is set, disabled when this bit is cleared. SPORT1 is con-

figured as a serial port when Bit 10 is set, or as flags and inter-

rupt lines when this bit is cleared. For proper operation of the

ADMC331, all other bits in this register must be cleared (which

is their default).

The DSP core has a wait state control register, MEMWAIT,

memory mapped at DM (0x3FFE). For proper operation of the

ADMC331, this register must always contain the value 0x8000

(which is the default).

The configuration of both the SYSCNTL and MEMWAIT

registers of the ADMC331 is shown at the end of the data sheet.

THREE-PHASE PWM CONTROLLER

Overview

The PWM generator block of the ADMC331 is a flexible, pro-

grammable, three-phase PWM waveform generator that can be

programmed to generate the required switching patterns to drive

a three-phase voltage source inverter for ac induction (ACIM),

or permanent magnet synchronous (PMSM) or a switched or

variable reluctance (SRM) motor control. In addition, the

PWM block contains special functions that considerably sim-

plify the generation of the required PWM switching patterns for

control of the electronically commutated motor (ECM) or

brushless dc motor (BDCM).

The PWM generator produces three pairs of PWM signals on

the six PWM output pins (AH, AL, BH, BL, CH and CL). The

six PWM output signals consist of three high side drive signals

(AH, BH and CH) and three low side drive signals (AL, BL and

CL). The polarity of the generated PWM signals may be

programmed by the PWMPOL pin, so that either active HI or

active LO PWM patterns can be produced by the ADMC331.

The switching frequency, dead time and minimum pulsewidths

of the generated PWM patterns are programmable using respec-

tively the PWMTM, PWMDT and PWMPD registers. In addi-

tion, three duty cycle control registers (PWMCHA, PWMCHB

and PWMCHC) directly control the duty cycles of the three

pair of PWM signals.

When the

PWMSR pin is pulled low, the PWM generator trans-

forms the six PWM output signals into six waveforms for

switched reluctance gate drive signals. The low side PWM

signals from the three-phase timing unit assume permanently

ON states, independent of the value written to the duty-cycle

registers. The duty cycles of the high side PWM signals from the

timing unit are still determined by the three duty-cycle registers.

Each of the six PWM output signals can be enabled or disabled

by separate output enable bits of the PWMSEG register. In

addition, three control bits of the PWMSEG register permit

crossover of the two signals of a PWM pair for easy control of

ECM or BDCM. In crossover mode, the PWM signal destined

for the high side switch is diverted to the complementary low

side output and the signal destined for the low side switch is

diverted to the corresponding high side output signal.

In many applications, there is a need to provide an isolation

barrier in the gate-drive circuits that turn on the power devices

of the inverter. In general, there are two common isolation

techniques, optical isolation using opto-couplers, and trans-

former isolation using pulse transformers. The PWM controller

of the ADMC331 permits mixing of the output PWM signals

with a high frequency chopping signal to permit easy interface to

such pulse transformers. The features of this gate-drive chop-

ping mode can be controlled by the PWMGATE register. There

is an 8-bit value within the PWMGATE register that directly con-

trols the chopping frequency. In addition, high frequency chopping

can be independently enabled for the high side and the low side

outputs using separate control bits in the PWMGATE register.

The PWM generator is capable of operating in two distinct

modes, single update mode or double update mode. In single

update mode, the duty cycle values are programmable only once

per PWM period, so that the resultant PWM patterns are sym-

metrical about the midpoint of the PWM period. In the double

update mode, a second updating of the PWM duty cycle values

is implemented at the midpoint of the PWM period. In this

mode, it is possible to produce asymmetrical PWM patterns,

that produce lower harmonic distortion in three-phase PWM

inverters. This technique also permits the closed loop controller

to change the average voltage applied to the machine winding at

a faster rate and so permits fast closed loop bandwidths to be

achieved. The operating mode of the PWM block (single or

double update mode) is selected by a control bit in MODECTRL

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