ADMC331BST datasheet(22/36 Pages) AD

22 / 36 page

ADMC331

–22–

REV. B

The entire interrupt control system of the ADMC331 is config-

ured and controlled by the IFC, IMASK and ICNTL registers

of the DSP core and the IRQFLAG register for the PWMSYNC

and PWMTRIP interrupts and PIOFLAG0, PIOFLAG1 and

PIOFLAG2 registers for the PIO interrupts.

Table IX. Interrupt Vector Addresses

Interrupt Vector

Interrupt Source

Address

Reset

0x0000 (Reserved)

PWMTRIP

0x002C (Highest Priority)

Peripheral Interrupt (

IRQ2)

0x0004

PWMSYNC

0x000C

PIO

0x0008

SPORT0 Transmit

0x0010

SPORT0 Receive

0x0014

Software Interrupt 1

0x0018

Software Interrupt 0

0x001C

SPORT1 Transmit Interrupt or

IRQ1

0x0020

SPORT1 Receive Interrupt or

IRQ0

0x0024

Timer

0x0028 (Lowest Priority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK

that must be set to enable the various interrupt sources. If any

peripheral interrupt is to be enabled, the

IRQ2 interrupt enable

bit (Bit 9) of the IMASK register must be set. The configuration

of the IMASK register of the ADMC331 is shown at the end of

the data sheet.

Interrupt Configuration

The IFC and ICNTL registers of the DSP core control and

configure the interrupt controller of the DSP core. The IFC

any of the eight DSP interrupts. Bits 0 to 7 of the IFC register

may be used to clear the DSP interrupts while Bits 8 to 15 can be

used to force a corresponding interrupt. Writing to Bits 11 and 12

in IFC is the only way to create the two software interrupts.

The ICNTL register is used to configure the sensitivity (edge-

or level-) of the

IRQ0, IRQ1 and IRQ2 interrupts and to enable/

disable interrupt nesting. Setting Bit 0 of ICNTL configures the

IRQ0 as edge-sensitive, while clearing the bit configures it for

level-sensitive. Bit 1 is used to configure the

IRQ1 interrupt

and Bit 2 is used to configure the

IRQ2 interrupt. It is recom-

mended that the

IRQ2 interrupt always be configured for level-

sensitive as this ensures that no peripheral interrupts are lost.

Setting Bit 4 of the ICNTL register enables interrupt nesting.

The configuration of both IFC and ICNTL registers is shown at

the end of the data sheet.

Interrupt Operation

Following a reset, the ROM code monitor of the ADMC331

copies a default interrupt vector table into program memory

RAM from address 0x0000 to 0x002F. Since each interrupt

source has a dedicated four-word space in this vector table, it is

possible to code short interrupt service routines (ISR) in place.

Alternatively, it may be required to insert a JUMP instruction to

the appropriate start address of the interrupt service routine if

more memory is required for the ISR.

On the occurrence of an interrupt, the program sequencer en-

sures that there is no latency (beyond synchronization delay)

when processing unmasked interrupts. In the case of the timer,

SPORT0, SPORT1 and software interrupts, the interrupt con-

troller automatically jumps to the appropriate location in the

interrupt vector table. At this point, a JUMP instruction to the

appropriate ISR is required.

In the event of a motor control peripheral interrupt, the opera-

tion is slightly different. When a peripheral interrupt is de-

tected, a bit is set in the IRQFLAG register for PWMSYNC

and

PWMTRIP or in the PIOFLAG0, or PIOFLAG1 or

PIOFLAG2 registers for a PIO interrupt, and the

IRQ2 line is

pulled low until all pending interrupts are acknowledged. For

any of the twenty six peripheral interrupts, the interrupt control-

ler automatically jumps to location 0x0004 in the interrupt

vector table. Code loaded at location 0x0004 by the monitor on

reset subsequently reads the IRQFLAG register to determine if

the source of the interrupt was a PWM trip, PWMSYNC or

PIOs and vectors to the appropriate interrupt vector location.

The code located at location 0x0004 by the monitor on reset is

as follows:

0x0004: ASTAT = DM(IRQFLAG);

DM(IRQFLAG_SAVE) = ASTAT;

IF EQ JUMP 0x002C

IF LT JUMP 0x000C;

At this point, a JUMP instruction to the appropriate ISR, at the

interrupt vector location shown in Table IX, is required. If

more than one interrupt occurs simultaneously, the higher prior-

ity interrupt service routine is executed. Reading the IRQFLAG

PWMTRIP and PWMSYNC bits and ac-

knowledges the interrupt, thus allowing further interrupts when

the ISR exits. When the IRQFLAG register is read, it is saved

in a data memory variable so the user ISR can check to see if

there are simultaneous PWMSYNC and

PWMTRIP interrupts.

A user’s PIO interrupt service routine must read the PIOFLAG0,

PIOFLAG1 and PIOFLAG2 registers to determine which PIO

port is the source of the interrupt. Reading PIOFLAG0,

PIOFLAG1 and PIOFLAG2 registers clear all bits in the regis-

ters and acknowledge the interrupt, thus allowing further inter-

rupts when the ISR exits.

The configuration of all these registers is shown at the end of

the data sheet.

SYSTEM CONTROLLER

The system controller block of the ADMC331 performs a num-

ber of distinct functions:

Manages the interface and data transfer between the DSP

core and the motor control peripherals.

Handles interrupts generated by the motor control periph-

erals and generates a DSP core interrupt signal

IRQ2.

Controls the ADC multiplexer select lines.

Enables

PWMTRIP and PWMSYNC interrupts.

Controls the multiplexing of the SPORT1 pins to select

either DR1A or DR1B data receive pins. It also allows

configuration of SPORT1 as a UART interface.

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