ADMC331BST datasheet(16/36 Pages) AD

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ADMC331

–16–

REV. B

where the subscript 1 refers to the value of that register during

the first half cycle and the subscript 2 refers to the value during

the second half cycle. The corresponding duty cycles are:

dAL

T AH

(PWMCHA1

+ PWMCHA

2 – PWMDT 1 – PWMDT 2 )

(PWMTM1

+ PWMTM

2 )

dAL

T AL

(PWMTM1

+ PWMTM

2 – PWMCHA1 – PWMCHA2 – PWMDT 1 – PWMDT 2 )

(PWMTM1

+ PWMTM

2 )

since for the completely general case in double update mode,

the switching period is given by:

= (PWMTM

+ PWMTM

2 )

× t

Again, the values of TAH and TAL are constrained to lie between

zero and TS.

Similar PWM signals to those illustrated in Figure 6 and Fig-

ure 7 can be produced on the BH, BL, CH and CL outputs by

programming the PWMCHB and PWMCHC registers in a man-

ner identical to that described for PWMCHA.

The PWM controller does not produce any PWM outputs until

all of the PWMTM, PWMCHA, PWMCHB and PWMCHC

registers have been written to at least once. Once these registers

have been written, internal counting of the timers in the three-

phase timing unit is enabled.

Effective PWM Resolution

In single update mode, the same value of PWMCHA, PWM-

CHB and PWMCHC are used to define the on-times in both

half cycles of the PWM period. As a result, the effective resolu-

tion of the PWM generation process is 2 tCK (or 76.9 ns for a

26 MHz CLKOUT) since incrementing one of the duty-cycle

registers by 1 changes the resultant on-time of the associated

PWM signals by tCK in each half period (or 2 tCK for the full

period).

In double update mode, improved resolution is possible since

different values of the duty cycles registers are used to define the

on-times in both the first and second halves of the PWM period.

As a result, it is possible to adjust the on-time over the whole

period in increments of tCK. This corresponds to an effective

PWM resolution of tCK in double update mode (or 38.5 ns for a

26 MHz CLKOUT).

The achievable PWM switching frequency at a given PWM

resolution is tabulated in Table V.

Table V. Achievable PWM Resolution in Single and Double

Update Modes

Resolution Single Update Mode

Double Update Mode

(Bit)

PWM Frequency (kHz)

50.7

101.5

25.4

50.7

12.7

25.4

6.3

12.7

3.2

6.3

Minimum Pulsewidth, PWMPD Register

In many power converter switching applications, it is desirable

to eliminate PWM switching signals below a certain width. It

takes a certain finite time to both turn on and turn off modern

power semiconductor devices. Therefore, if the width of any of

the PWM signals goes below some minimum value, it may be

desirable to completely eliminate the PWM switching for that

particular cycle.

The allowable minimum on-time for any of the six PWM out-

puts over half a PWM period that can be produced by the PWM

controller may be programmed using the 10-bit read/write

PWMPD register. The minimum on-time is programmed in

increments of tCK so that the minimum on-time that will be

produced over any half PWM period, TMIN, is related to the

value in the PWMPD register by:

T MIN

= PWMPD × t

so that a PWMPD value of 0x002 defines a permissible mini-

mum on-time of 76.9 ns for a 26 MHz CLKOUT.

In each half cycle of the PWM, the timing unit checks the on-

time of each of the six PWM signals. If any of the times are

found to be less than the value specified by the PWMPD regis-

ter, the corresponding PWM signal is turned OFF for the entire

half period and its complementary signal is turned completely

ON.

Consider the example where PWMTM = 200, PWMCHA = 5,

PWMDT = 3, PWMPD = 10 with a CLKOUT of 26 MHz

and operation in single update mode. In this case, the PWM

switching frequency is 65 kHz and the dead time is 230 ns.

The permissible on-time of any PWM signal over one half of

any period is 384.6 ns. Clearly, for this example, the dead

time adjusted on-time of the AH signal over half a PWM

period is (5–3)

× 38.5 ns = 77 ns. This is less than the permis-

sible value, so the timing unit will output a completely OFF

(0% duty cycle) signal on AH. Additionally, the AL signal will

be turned ON for the entire half period (100% duty cycle).

Switched Reluctance Mode

The PWM block of the ADMC331 contains a switched reluc-

tance mode that is controlled by the state of the

PWMSR pin.

The switched reluctance (SR) mode is enabled by connecting

the

PWMSR pin to GND. In this SR mode, the low side PWM

signals from the three-phase timing unit assume permanently

ON states, independent of the value written to the duty-cycle

registers. The duty cycles of the high side PWM signals from

the timing unit are still determined by the three duty-cycle regis-

ters. Using the crossover feature of the output control unit, it is

possible to divert the permanently ON PWM signals to either

the high side or the low side outputs. This mode is necessary

because in the typical power converter configuration for switched

or variable reluctance motors, the motor winding is connected

between the two power switches of a given inverter leg. There-

fore, in order to build up current in the motor winding, it is

necessary to turn on both switches at the same time. Typical

active LO PWM signals during operation in SR mode are shown

in Figure 8 for operation in double update mode. It is clear that

the three low side signals (AL, BL and CL) are permanently ON

and the three high side signals are modulated so that the corre-

sponding high side power switches are switched between the ON

and OFF states.

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