ADMC331

–33–

REV. B

0

0

0

0

0

0

00

0

0

0

SYSSTAT (R)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0 = LOW

1 = HIGH

DM (0x2016)

0 = NORMAL

1 = WATCHDOG RESET

OCCURRED

PWMTRIP

PIN STATUS

0 = LOW

1 = HIGH

WATCHDOG

STATUS

PWMPOL PIN

STATUS

PWMSR

PIN STATUS

1 = SR MODE

0 = NORMAL

PWM TIMER

STATUS

0 = 1ST HALF OF PWM

CYCLE

1 = 2ND HALF OF PWM

CYCLE

0

0

00

0

0

0

00

0

0

00

0

0

0

MODECTRL (R/W)

DM (0x2015)

SPORT1 DATA

RECEIVE SELECT

0 = DR1A

1 = DR1B

0 = SPORT

1 = UART

SPORT1 MODE

SELECT

PWM UPDATE MODE

SELECT

0 = SINGLE UPDATE MODE

1 = DOUBLE UPDATE MODE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ADC MUX CONTROL

00 VAUX0

01 VAUX1

10 VAUX2

11 VAUX3

PWMTRIP

INTERRUPT

0 = DISABLE

1 = ENABLE

PWMSYNC

INTERRUPT

0 = DISABLE

1 = ENABLE

AUXILIARY

PWM SELECT

0 = OFFSET MODE

1 = INDEPENDENT MODE

ADC

COUNTER

SELECT

0 = 1/2 DSP CLOCKOUT

FREQUENCY

1 = DSP CLOCKOUT

FREQUENCY

0

0

00

0

0

0

00

0

0

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

00

IRQFLAG (R)

PWMTRIP

1 = ACTIVE

PWMSYNC 1 = ACTIVE

DM (0x2017)

0

0

0

0

0

0

00

0

0

00

0

0

00

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

WDTIMER (W)

DM (0x2018)

Figure 22. Configuration of ADMC331 Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.