ADMC331BST datasheet(14/36 Pages) AD

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ADMC331

–14–

REV. B

These registers, in conjunction with the three 16-bit duty-cycle

registers (PWMCHA, PWMCHB and PWMCHC), control the

output of the three-phase timing unit.

PWM Switching Frequency, PWMTM Register

The PWM switching frequency is controlled by the 16-bit read/

write PWM period register, PWMTM. The fundamental timing

unit of the PWM controller is tCK (DSP instruction rate).

Therefore, for a 26 MHz CLKOUT, the fundamental time

increment is 38.5 ns. The value written to the PWMTM regis-

ter is effectively the number of tCK clock increments in half a

PWM period. The required PWMTM value is a function of the

desired PWM switching frequency (fPWM) and is given by:

PWMTM

f CLKOUT

× f

PWM

f CLKIN

f PWM

Therefore, the PWM switching period, TS, can be written as:

= 2 × PWMTM × t

For example, for a 26 MHz CLKOUT and a desired PWM

switching frequency of 10 kHz (TS = 100

µs), the correct value

to load into the PWMTM register is:

PWMTM

×106

×10 ×103

=1300

The largest value that can be written to the 16-bit PWMTM

PWM switching frequency of:

f PWM,min

×106

×65,535

=198.4 Hz

PWM Switching Dead Time, PWMDT Register

The second important parameter that must be set up in the

initial configuration of the PWM block is the switching dead

time. That is a short delay time introduced between turning off

one PWM signal (AH) and turning on the complementary sig-

nal, AL. This short time delay is introduced to permit the

power switch being turned off (AH in this case) to completely

recover its blocking capability before the complementary switch

is turned on. This time delay prevents a potentially destructive

short-circuit condition from developing across the dc link ca-

pacitor of a typical voltage source inverter.

The dead time is controlled by the 10-bit, read/write PWMDT

dead time inserted into the three pairs of PWM output signals.

The dead time, TD, is related to the value in the PWMDT regis-

ter by:

T D

= PWMTM × 2 × t

Therefore, a PWMDT value of 0x00A (= 10), introduces a

769.2 ns delay between the turn-off on any PWM signal (AH)

and the turn-on of its complementary signal (AL). The amount

of the dead time can therefore be programmed in increments of

2tCK (or 76.92 ns for a 26 MHz CLKOUT). The PWMDT

(=1023) corresponding to a maximum programmed dead time

of:

TD,max = 1023

× 2 × tCK = 1023 × 2 × 38.46 × 10–9 = 78.69

µs

for a CLKOUT rate of 26 MHz. Obviously, the deadtime can

be programmed to be zero by writing 0 to the PWMDT register.

PWM Operating Mode, MODECTRL and SYSSTAT Registers

The PWM controller of the ADMC331 can operate in two

distinct modes: single update mode and double update mode.

The operating mode of the PWM controller is determined by

the state of Bit 6 of the MODECTRL register. If this bit is

cleared, the PWM operates in the single update mode. Setting

Bit 6 places the PWM in the double update mode. By default,

following either a peripheral reset or power on, Bit 6 of the

MODECTRL register is cleared so that the default operating

mode is in single update mode.

In single update mode, a single PWMSYNC pulse is produced

in each PWM period. The rising edge of this signal marks the

start of a new PWM cycle and is used to latch new values from

the PWM configuration registers (PWMTM, PWMDT, PWMPD

and PWMSYNCWT) and the PWM duty-cycle registers

(PWMCHA, PWMCHB and PWMCHC) into the three-phase

timing unit. In addition, the PWMSEG register is also latched

into the output control unit on the rising edge of the PWMSYNC

pulse. In effect, this means that the characteristics and resultant

duty cycles of the PWM signals can be updated only once per

PWM period at the start of each cycle. The result is that PWM

patterns that are symmetrical about the midpoint of the switch-

ing period are produced.

In double update mode, there is an additional PWMSYNC

pulse produced at the midpoint of each PWM period. The rising

edge of this new PWMSYNC pulse is again used to latch new

values of the PWM configuration registers, duty-cycle registers

and the PWMSEG register. As a result it is possible to alter

both the characteristics (switching frequency, dead time, minimum

pulsewidth and PWMSYNC pulsewidth) as well as the output

duty cycles at the midpoint of each PWM cycle. Consequently, it is

possible to produce PWM switching patterns that are no longer

symmetrical about the midpoint of the period (asymmetrical

PWM patterns).

In the double update mode, it may be necessary to know whether

operation at any point in time is in either the first half or the

second half of the PWM cycle. This information is provided by

Bit 3 of the SYSSTAT register, which is cleared during opera-

tion in the first half of each PWM period (between the rising

edge of the original PWMSYNC pulse and the rising edge of

the new PWMSYNC pulse introduced in double update mode).

Bit 3 of the SYSSTAT register is set during operation in the

second half of each PWM period. This status bit allows the user

to make a determination of the particular half-cycle during

implementation of the PWMSYNC interrupt service routine, if

required.

The advantage of the double update mode is that lower har-

monic voltages can be produced by the PWM process and faster

control bandwidths are possible. However, for a given PWM

switching frequency, the PWMSYNC pulses occur at twice the

rate in the double update mode. Since new duty cycle values

must be computed in each PWMSYNC interrupt service rou-

tine, there is a larger computational burden on the DSP in the

double update mode.

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