STM32F102XB datasheet(48/76 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F102x8, STM32F102xB

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Doc ID 15056 Rev 4

5.3.12

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product

operation. However, in order to give an indication of the robustness of the microcontroller in

cases when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into the

I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of spec current injection on adjacent pins or other functional failure (for

example reset, oscillator frequency deviation).

The test results are given in Table 33.

5.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 34 are derived from tests

performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL

compliant.

Table 33.

I/O current injection susceptibility

Symbol

Description

Functional susceptibility

Unit

Negative

injection

Positive

injection

IINJ

Injected current on OSC_IN32,

OSC_OUT32, PA4, PA5, PC13

-0

Injected current on all FT pins

-5

Injected current on any other pin

-5

Table 34.

I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Standard I/O input low level

voltage

–0.3

0.28 (VDD– 2)

+ 0.8

I/O FT(1) input low level voltage

–0.3

0.32 (VDD– 2)

+ 0.75

VIH

Standard I/O input high level

voltage

0.41 (VDD– 2)

+ 1.3

-VDD+0.5

I/O FT(1) input high level voltage

VDD > 2 V

0.42 (VDD– 2)

+ 1.0

-5.5

VDD ≤ 2V

5.2

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