ADE7953 datasheet(43/68 Pages) AD

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Data Sheet

ADE7953

Rev. A | Page 43 of 68

ZERO-CROSSING DETECTION

The ADE7953 includes a zero-crossing (ZX) detection feature

on all three input channels. Zero-crossing detection allows

measurements to be synchronized to the frequency of the

incoming waveforms.

Zero-crossing detection is performed at the output of LPF1 to

ensure that no harmonics or distortion affect the accuracy of the

zero-crossing measurement. LPF1 is a single-pole filter with a

−3 dB cutoff of 80 Hz and is clocked at 223 kHz. The phase shift

of this filter therefore results in a time delay of approximately

2.2 ms (39.6°) at 50 Hz. To assure good resolution of the ZX

detection, LPF1 cannot be disabled. Figure 61 shows how the

zero-crossing signal is detected.

GAIN[23:0]

REFERENCE

HPFEN BIT

DSP

HPF

PGA

ADC

IA, IB,

OR V

DETECTION

LPF1

IA, IB, OR V

39.6° OR 2.2ms @ 50Hz

LPF1 OUTPUT

Figure 61. Zero-Crossing Detection

The error in the ZX detection is 0.08° for 50 Hz systems and

0.09° for 60 Hz systems. The zero-crossing information is

available on both an output pin or via an interrupt.

ZERO-CROSSING OUTPUT PINS

By default, the voltage and current channel ZX information is

configured to be output on Pin 1 (ZX) and Pin 21 (ZX_I),

respectively. These dedicated output pins provide an unlatched

ZX indicator (see the Alternative Output Functions section).

Voltage Channel Zero Crossing

The voltage channel zero-crossing indicator is output on Pin 1

(ZX) by default. Figure 62 shows the operation of the ZX output.

2.2ms @ 50Hz

Figure 62. Voltage Channel ZX Output

As shown in Figure 62, the ZX output pin goes high on the

positive-going edge of the voltage channel zero crossing and

low on the negative-going edge of the zero crossing. A delay

of approximately 2.2 ms should be expected on this pin due to

the time delay of LPF1.

Current Channel Zero Crossing

The current channel zero-crossing indicator is output on Pin 21

(ZX_I) by default. The ZX_I pin operates in a similar way to the

ZX pin (see Figure 62). The ZX_I pin goes high on the positive-

going edge of the current channel zero crossing and low on the

negative-going edge of the current channel zero crossing. By

default, the ZX_I pin is triggered based on Current Channel A.

The ZX_I pin can be configured to trigger based on Current

Channel B by setting the ZX_I bit (Bit 11) of the CONFIG

ZERO-CROSSING INTERRUPTS

Three interrupts are associated with zero-crossing detection, one

for each input channel: Current Channel A, Current Channel B,

and the voltage channel. The zero-crossing condition occurs

when either a positive or a negative zero-crossing transition

takes place. If this transition occurs on the voltage channel, the

ZXV bit (Bit 15) of the IRQSTATA register (Address 0x22D and

Address 0x32D) is set to 1. If this transition occurs on Current

Channel A, the ZXIA bit (Bit 12) of the IRQSTATA register is

set to 1. If this transition occurs on Current Channel B, the

ZXIB bit (Bit 12) of the IRQSTATB register (Address 0x230 and

Address 0x330) is set to 1. Figure 63 shows the operation of the

voltage channel zero-crossing interrupt.

ZXV (BIT 15) OF

IRQSTATA REGISTER

Figure 63. Zero-Crossing Interrupt

As shown by the dotted line in Figure 63, the ADE7953 can be

configured to trigger a zero-crossing event on only the positive-

going or the negative-going zero crossing. The ZX_EDGE bits

(Bits[13:12]) of the CONFIG register (Address 0x102) set the

edge that triggers the zero-crossing event. These bits default to

00 (the zero-crossing event is triggered on both the positive-

going and negative-going edges). Changing the ZX_EDGE bits

affects the zero-crossing event on all three channels. Note that

changing the ZX_EDGE bits affects only the ZX status bits and

interrupts; the function of the ZX pin (Pin 1) and the ZX_I pin

(Pin 21) is not affected.

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