ADE7953 datasheet(6/68 Pages) AD

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ADE7953

Data Sheet

Rev. A | Page 6 of 68

TIMING CHARACTERISTICS

SPI Interface Timing

VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter

Description

Min1

Max1

Unit

tCS

CS to SCLK edge

tSCLK

SCLK period

200

tSL

SCLK low pulse width

tSH

SCLK high pulse width

tDAV

Data output valid after SCLK edge

tDSU

Data input setup time before SCLK edge

tDHD

Data input hold time after SCLK edge

tDF

Data output fall time

tDR

Data output rise time

tSR

SCLK rise time

tSF

SCLK fall time

tDIS

MISO disabled after CS rising edge

tSFS

CS high after SCLK edge

tSFS_LK

CS high after SCLK edge (when writing to

COMM_LOCK bit)

1200

1 Min and max values are typical minimum and maximum values.

SPI Interface Timing Diagram

LSB IN

INTERMEDIATE BITS

tSFS_LK

tSFS

tDIS

tCS

tSL

tDF

tSH

tDHD

tDAV

tDSU

tSR

tSF

tDR

tSCLK

MSB IN

MOSI

MISO

SCLK

MSB OUT

LSB OUT

Figure 2. SPI Interface Timing

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