ADE7953 datasheet(56/68 Pages) AD

56 / 68 page

ADE7953

Data Sheet

Rev. A | Page 56 of 68

UART Read

A read from the ADE7953 via the UART interface is initiated by

the master sending a packet of three frames. If the first frame

has the value 0x35, a read is being issued. The second and third

frames contain the address of the register being accessed. When

the ADE7953 receives a legal packet, it decodes the command

(see Figure 73).

The frame time is 2.08 ms. A frame-to-frame delay (t1) of 4 ms

max provides a 50% buffer on the frame time without needlessly

slowing the communication. When the read packet is decoded,

the ADE7953 sends the data from the selected register out on the

Tx pin (see F4 and F5 in Figure 73). This occurs approximately

0.1 ms after the complete frame is received. This data can be 1,

2, 3, or 4 bytes long, depending on the size of the register that is

being accessed. The register data is sent LSB first. After the last

frame of register data is sent from the ADE7953, a packet-to-

packet delay (t2) of 6 ms min is required before any incoming

data on the Rx pin is accepted. This packet-to-packet timeout

ensures that no overlap is possible.

UART Write

A write to the ADE7953 via the UART interface is initiated by

the master sending a packet of three frames. If the first frame

has the value 0xCA, a write is being issued. The second and

third frames contain the address of the register being accessed.

The next two frames contain the data to be written. When the

ADE7953 receives a legal packet, it decodes the command as

follows:

•

If the number of frames obtained after the initial packet is

the same as the size of the register specified by F2 and F3, the

packet is legal and the corresponding register is written.

•

If the number of frames does not equal the size of the

specified register, the command is illegal and no further

action is taken.

After the last frame of data is received on the Rx pin, a wait

period of t2 is required before any incoming data on the Rx pin

is treated as a new packet. This operation is shown in Figure 74.

READ/

WRITE

ADDRESS

MSB

ADDRESS

LSB

READ/

WRITE

ADDRESS

MSB

DATA

LSB

DATA

MSB

Figure 73. UART Read

READ/

WRITE

ADDRESS

MSB

ADDRESS

LSB

READ/

WRITE

ADDRESS

MSB

DATA

LSB

DATA

MSB

Figure 74. UART Write

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