ADE7953 datasheet(26/68 Pages) AD

26 / 68 page

ADE7953

Data Sheet

Rev. A | Page 26 of 68

Active Energy Line Cycle Accumulation Mode

The number of half line cycles written to the LINECYC register

is used for both the Current Channel A and Current Channel B

accumulation periods. At the end of a line cycle accumulation

cycle, the AENERGYA and AENERGYB registers are updated,

and the CYCEND flag is set in the IRQSTATA register (Address

0x22D and Address 0x32D). If the CYCEND bit in the IRQENA

this way, the IRQ pin can also be used to signal the completion of

the line cycle accumulation. Another accumulation cycle begins

immediately as long as the ALWATT and BLWATT bits in the

LCYCMODE register remain set.

In active energy line cycle accumulation mode, the energy

accumulation of the ADE7953 is synchronized to the voltage

channel zero crossing so that the active energy can be accumu-

lated over an integral number of half line cycles. This feature is

available for both Current Channel A and Current Channel B

active energy. The advantage of summing the active energy over

an integral number of half line cycles is that the sinusoidal

component of the active energy is reduced to 0 (see Equation 12

to Equation 15). This eliminates any ripple in the energy calcula-

tion. Energy is calculated more accurately and in a shorter time

because the integration period can be shortened. The line cycle

accumulation mode can be used for fast calibration and also to

obtain the average power over a specified time period. Using

Equation 6, the following description of the energy accumulation

can be derived:

P(t)

= VI – [LPF] × cos(2ωt)

(12)

ωt

LPF

VIdt

∫∫

−

)

cos(

]

[

)

(

(13)

The contents of the AENERGYA and AENERGYB registers are

updated synchronous to the CYCEND flag. The AENERGYA and

AENERGYB registers hold their current values until the end of

the next line cycle period, when the contents are replaced with

the new reading. If the read-with-reset bit (RSTREAD) in the

LCYCMODE register (Address 0x004) is set, the contents of the

AENERGYA and AENERGYB registers are cleared after a read

and remain at 0 until the end of the next line cycle period.

where:

n is an integer.

T is the line cycle period.

Because the sinusoidal component is integrated over an integer

number of line cycles, its value is always 0. Therefore,

∫

VIdt

E(t)

(14)

If a new value is written to the LINECYC register (Address 0x101)

midway through a line cycle accumulation, the new value is not

internally loaded until the end of a line cycle period. When the

LINECYC register is updated mid-reading, the current energy

accumulation cycle is completed, and the new value is then

programmed, ready for the next cycle. This prevents any invalid

readings due to changes to the LINECYC register (see Figure 47).

E = VInt

(15)

AENERGYx REGISTER

CYCEND IRQ

LINECYC REGISTER

NEW LINE CYCLE

VALUE PROGRAMMED

INTERNAL LINE CYCLE

UPDATED

Line cycle accumulation mode is disabled by default and can be

enabled on Current Channel A and Current Channel B by setting

the ALWATT and BLWATT bits to 1 in the LCYCMODE register

(Address 0x004). The accumulation time should be written to

the LINECYC register (Address 0x101) in the unit of number of

half line cycles. The ADE7953 can accumulate energy for up to

65,535 half line cycles. This equates to an accumulation period

of approximately 655 sec with 50 Hz inputs and 546 sec with

60 Hz inputs.

Figure 47. Changing the LINECYC Register

xWGAIN

xWATTOS

INTERNAL

ACCUMULATION

FIXED INTERNAL

THRESHOLD

CALIBRATION

CONTROL

ZERO-CROSSING

DETECTION

OUTPUT FROM

VOLTAGE CHANNEL

ADC

OUTPUT FROM

LPF2

AENERGYx

LPF1

LINECYC

Figure 48. Active Energy Line Cycle Accumulation

ADE7953 数据表(PDF) 26 Page - Analog Devices

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