ADE7953 datasheet(32/68 Pages) AD

32 / 68 page

ADE7953

Data Sheet

Rev. A | Page 32 of 68

xVAOS

INTERNAL

ACCUMULATION

FIXED INTERNAL

THRESHOLD

CALIBRATION

CONTROL

ZERO-CROSSING

DETECTION

OUTPUT FROM

VOLTAGE CHANNEL

ADC

APPARENT

POWER

SIGNAL

APENERGYx

LINECYC

LPF1

xVAGAIN

Figure 56. Apparent Energy Line Cycle Accumulation

Apparent Energy Line Cycle Accumulation Mode

In apparent energy line cycle accumulation mode, the energy

accumulation of the ADE7953 is synchronized to the voltage

channel zero crossing so that the apparent energy on Current

Channel A and Current Channel B can be accumulated over

an integral number of half line cycles. Line cycle accumulation

mode is disabled by default and can be enabled on Current

Channel A and Current Channel B by setting the ALVA and

BLVA bits to 1 in the LCYCMODE register (Address 0x004).

The accumulation time should be written to the LINECYC

The number of half line cycles written to the LINECYC register

is used for both the Current Channel A and Current Channel B

accumulation periods. The ADE7953 can accumulate apparent

energy for up to 65,535 half line cycles. This equates to an accu-

mulation period of approximately 655 sec with 50 Hz inputs

and 546 sec with 60 Hz inputs.

At the end of a line cycle accumulation cycle, the APENERGYA

and APENERGYB registers are updated, and the CYCEND flag

in the IRQSTATA register (Address 0x22D and Address 0x32D)

is set. If the CYCEND bit in the IRQENA register is set, an external

interrupt is issued on the IRQ pin. In this way, the IRQ pin can

also be used to signal the completion of the line cycle accumula-

tion. Another accumulation cycle begins immediately, as long as

the ALVA and BLVA bits in the LCYCMODE register remain set.

The contents of the APENERGYA and APENERGYB registers

are updated synchronous to the CYCEND flag. The APENERGYA

and APENERGYB registers hold their current values until the

end of the next line cycle period, when the contents are replaced

with the new reading. If the read-with-reset bit (RSTREAD) in

the LCYCMODE register (Address 0x004) is set, the contents of

the APENERGYA and APENERGYB registers are cleared after

a read and remain at 0 until the end of the next line cycle period.

If a new value is written to the LINECYC register (Address 0x101)

midway through a line cycle accumulation, the new value is not

internally loaded until the end of a line cycle period. When the

LINECYC register is updated mid-reading, the current energy

accumulation cycle is completed, and the new value is then

programmed, ready for the next cycle. This prevents any invalid

readings due to changes to the LINECYC register (see Figure 47).

Note that when line cycle accumulation mode is first enabled, the

reading after the first CYCEND flag should be ignored because

it may be inaccurate. This is because the line cycle accumulation

mode is not synchronized to the zero crossing and, therefore,

the first reading may not be over a complete number of half line

cycles. After the first line cycle accumulation is complete, all

successive readings will be correct.

AMPERE-HOUR ACCUMULATION

In a tampering situation where no voltage is available to the energy

meter, the ADE7953 can accumulate the ampere-hour measure-

ment instead of the apparent power in the APENERGYA and

APENERGYB registers. If enabled, the Current Channel A and

Current Channel B IRMS measurements are continually accu-

mulated instead of the apparent power. If enabled, the apparent

power CF output pin also reflects the ampere-hour measurement

(see the Energy-to-Frequency Conversion section). All the signal

processing and calibration registers available for the apparent

power and apparent energy accumulation remain active when

the ampere-hour accumulation mode is enabled. This includes

the apparent energy no-load feature (see the Apparent Energy

No-Load section). Recalibration is required in this mode due to

internal scaling differences between the IRMS and apparent

signals.

ADE7953 数据表(PDF) 32 Page - Analog Devices

ADE7953 数据表(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载