ADE7953 datasheet(48/68 Pages) AD

48 / 68 page

ADE7953

Data Sheet

Rev. A | Page 48 of 68

OVERCURRENT AND OVERVOLTAGE DETECTION

The ADE7953 provides an overcurrent and overvoltage feature

that detects whether the absolute value of the current or voltage

waveform exceeds a programmable threshold. This feature uses

the instantaneous voltage and current signals. The two registers

associated with this feature, OVLVL (Address 0x224 and

Address 0x324) and OILVL (Address 0x225 and Address 0x325),

are used to set the voltage and current channel thresholds, respec-

tively. The OILVL threshold register determines the threshold

for both the Current Channel A and Current Channel B over-

current features. The same threshold must therefore be used for

both Current Channel A and Current Channel B. The default

value of the OVLVL and OILVL registers is 0xFFFFFF, which

effectively disables the feature. Figure 66 shows the operation of

the overvoltage detection feature.

OV RESET

LOW WHEN

RSTIRQSTATA

IS READ

OVLVL

OV (BIT 16) OF

IRQSTATA REGISTER

Figure 66. Overvoltage Detection

As shown in Figure 66, if the ADE7953 detects an overvoltage

condition, the OV bit (Bit 16) of the IRQSTATA register

(Address 0x22D and Address 0x32D) is set to 1. This bit can be

cleared by reading the RSTIRQSTATA register (Address 0x22E

and Address 0x32E). The overcurrent detection feature works in

a similar manner (see Figure 67).

OIA RESET LOW

WHEN RSTIRQSTATA

OILVL

OIA (BIT 13) OF

IRQSTATA

OILVL

OIB (BIT 13) OF

IRQSTATB

OIB RESET LOW

WHEN RSTIRQSTATB

Figure 67. Overcurrent Detection

As shown in Figure 67, if an overcurrent condition is detected

on Current Channel A, the OIA bit (Bit 13) of the IRQSTATA

RSTIRQSTATA register. If an overcurrent condition is detected

on Current Channel B, the OIB bit (Bit 13) of the IRQSTATB

can be cleared by reading from the RSTIRQSTATB register

(Address 0x231 and Address 0x331).

SETTING THE OVLVL AND OILVL REGISTERS

The 24-bit/32-bit unsigned OVLVL and OILVL registers map

directly to the VPEAK (Address 0x226 and Address 0x326)

and IAPEAK (Address 0x228 and Address 0x328) registers,

respectively (see the Peak Detection section). Note that after

gain calibration, Current Channel A and Current Channel B are

matched and, therefore, the IAPEAK and IBPEAK registers are

matched with common inputs. The settings of the OVLVL and

OILVL registers should be based on the VPEAK and IAPEAK

readings with full-scale inputs.

To set the OVLVL register, the maximum voltage input should

be applied and a reading taken from the RSTVPEAK register

(Address 0x227 and Address 0x327). This resets the voltage peak

reading. After a wait period of a few line cycles, the VPEAK

determine the voltage peak. This reading should then be scaled

to the amplitude required for overvoltage detection. For example,

if an overvoltage threshold of 120% of the maximum voltage is

required, the peak reading should be multiplied by 1.2 and the

resulting value written to the OVLVL register. This method ensures

that an accurate threshold is set for each individual design.

OVERVOLTAGE AND OVERCURRENT INTERRUPTS

Three interrupts are associated with the overvoltage and

overcurrent features. The first interrupt is associated with the

overvoltage feature; it is enabled by setting the OV bit (Bit 16)

of the IRQENA register (Address 0x22C and Address 0x32C).

When this bit is set, an overvoltage condition causes the

external IRQ pin to be pulled low.

A second interrupt is associated with the overcurrent detection

feature on Current Channel A. This interrupt is enabled by

setting the OIA bit (Bit 13) of the IRQENA register. When this

bit is set, an overcurrent condition on Current Channel A

causes the external IRQ pin to be pulled low.

The third interrupt is associated with the overcurrent detection

feature on Current Channel B. This interrupt is enabled by setting

the OIB bit (Bit 13) of the IRQENB register (Address 0x22F and

Address 0x32F). When this bit is set, an overcurrent condition

on Current Channel B causes the IRQ alternative output to be

triggered, if the alternative output is enabled (see the

section).

Current

Channel B Interrupts

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