LCMXO2-256ZE-3TG100C datasheet(34/106 Pages) LATTICE

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Architecture

MachXO2 Family Data Sheet

There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes:

• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology (Appendix B)

• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices

Figure 2-22. SPI Core Block Diagram

Table 2-16 describes the signals interfacing with the SPI cores.

Table 2-16. SPI Core Signal Description

Hardened Timer/Counter

MachXO2 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional,

16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter sup-

ports the following functions:

Signal Name

I/O

Master/Slave

Description

spi_csn[0]

Master

SPI master chip-select output

spi_csn[1..7]

Master

Additional SPI chip-select outputs (total up to eight slaves)

spi_scsn

Slave

SPI slave chip-select input

spi_irq

Master/Slave

Interrupt request

spi_clk

I/O

Master/Slave

SPI clock. Output in master mode. Input in slave mode.

spi_miso

I/O

Master/Slave

SPI data. Input in master mode. Output in slave mode.

spi_mosi

I/O

Master/Slave

SPI data. Output in master mode. Input in slave mode.

ufm_sn

Slave

Configuration Slave Chip Select (active low), dedicated for selecting the

User Flash Memory (UFM).

cfg_stdby

Master/Slave

Stand-by signal – To be connected only to the power module of the MachXO2

device. The signal is enabled only if the “Wakeup Enable” feature has been

set within the EFB GUI, SPI Tab.

cfg_wake

Master/Slave

Wake-up signal – To be connected only to the power module of the MachXO2

device. The signal is enabled only if the “Wakeup Enable” feature has been

set within the EFB GUI, SPI Tab.

EFB

SPI Function

Core

Logic/

Routing

EFB

WISHBONE

Interface

SPI

Registers

Control

Logic

Configuration

Logic

MISO

MOSI

SCK

MCSN

SCSN

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