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LCMXO2-256ZE-3TG100C 数据表(PDF) 12 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3TG100C 数据表(HTML) 12 Page - Lattice Semiconductor |
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12 / 106 page  2-8 Architecture MachXO2 Family Data Sheet The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2-7. The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock. This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied. The MachXO2 also has a feature that allows the user to select between two different reference clock sources dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are shown in the table. The MachXO2 PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are updated through the WISHBONE port the PLL may lose lock and not relock until the tLOCK parameter has been sat- isfied. The timing parameters for the PLL are shown in the table. For more details on the PLL and the WISHBONE interface, see TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide. Figure 2-7. PLL Diagram CLKOP, CLKOS, CLKOS2, CLKOS3 REFCLK Internal Feedback FBKSEL CLKOP CLKOS 4 CLKOS2 CLKOS3 REFCLK Divider M (1 - 40) LOCK ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3 RST, RESETM, RESETC, RESETD CLKFB CLKI Dynamic Phase Adjust PHASESEL[1:0] PHASEDIR PHASESTEP FBKCLK Divider N (1 - 40) Fractional-N Synthesizer Phase detector, VCO, and loop filter. CLKOS3 Divider (1 - 128) CLKOS2 Divider (1 - 128) Phase Adjust Phase Adjust Phase Adjust/ Edge Trim CLKOS Divider (1 - 128) CLKOP Divider (1 - 128) Lock Detect ClkEn Synch ClkEn Synch ClkEn Synch ClkEn Synch PLLDATO[7:0] , PLLACK PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0] A0 B0 C0 D0 D1 Mux A2 Mux B2 Mux C2 Mux D2 Mux DPHSRC Phase Adjust/ Edge Trim STDBY |
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